Revision as of 05:34, 23 July 2017

Template:mpu R-Car M3 is a 64-bit hepta-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The M3 incorporates four Cortex-A53 cores, two Cortex-A57, and an additional Cortex-R7 core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6250 GPU.

Cache

Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 480 KiB 491,520 B 0.469 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 2x48+5x32 KiB     L1D$ 224 KiB 229,376 B 0.219 MiB 7x32 KiB     L2$ 1.5 MiB 1,536 KiB 1,572,864 B 0.00146 GiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4-3200 Supports ECC No Controllers 1 Channels 2 Width 32 bit Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 5.96 GiB/s Double 11.92 GiB/s

Expansions

• USB 3.0 host interface (DRD) × 1 port (wPHY)
• USB 2.0 host interface × 1 port (wPHY)
• USB 2.0 host/function/OTG interface × 1 port (wPHY)
• SD host interface × 4 ch (SDR104)
• Multimedia card interface × 2 ch
• PCI Express 2.0 (1 lane) x 2 ch
• Media local bus (MLB) interface × 1 ch (3-pin interface)
• Controller area network (CAN-FD support) interface × 2ch
• Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
• I2C bus interface × 8 ch
• Serial communication interface (SCIF) × 11 ch
• SPI multi I/O bus controller (RPC) × 1 ch (HyperFlashTM/QSPI support)
• Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
• Digital radio interface (DRIF) × 4 ch

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR GX6250 Designer Imagination Technologies

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	VFPv4 Vector Floating Point (VFP) v4 Extension NEON Advanced SIMD extension TrustZone TrustZone Security Extensions

Block Diagram