Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i7/i7-8600u"
(initial page for the 8600U, engineering samples are well into circulation) |
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|bus type=OPI | |bus type=OPI | ||
|bus rate=4 GT/s | |bus rate=4 GT/s | ||
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|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
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|technology=CMOS | |technology=CMOS | ||
|word size=64 bit | |word size=64 bit | ||
| − | |core count= | + | |core count=4 |
| − | |thread count= | + | |thread count=8 |
|max cpus=1 | |max cpus=1 | ||
|max memory=32 GiB | |max memory=32 GiB | ||
Revision as of 03:08, 16 July 2017
Template:mpu Core i7-8600U is a 64-bit quad-core high-end performance x86 mobile microprocessor set to be introduced by Intel in late 2017. This chip, which is based on the Coffee Lake microarchitecture, is fabricated on Intel's 14nm++ process. The i7-8600U operates at ? GHz with a TDP of 15 W supporting a Turbo Boost frequency of ? GHz. The processor supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory.
Cache
- Main article: Coffee Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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This section is empty; you can help add the missing info by editing this page. |
Features
[Edit/Modify Supported Features]
