From WikiChip
					
    Difference between revisions of "intel/core i7/i7-6700hq"    
                	
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|l3 break=4x1.5 MiB  | |l3 break=4x1.5 MiB  | ||
|l3 policy=write-back  | |l3 policy=write-back  | ||
| + | }}  | ||
| + | |||
| + | == Memory controller ==  | ||
| + | {{memory controller  | ||
| + | |type=LPDDR3-1866  | ||
| + | |type 2=DDR3L-1600  | ||
| + | |type 3=DDR4-2133  | ||
| + | |ecc=No  | ||
| + | |max mem=64 GiB  | ||
| + | |controllers=1  | ||
| + | |channels=2  | ||
| + | |max bandwidth=31.79 GiB/s  | ||
| + | |bandwidth schan=15.89 GiB/s  | ||
| + | |bandwidth dchan=31.79 GiB/s  | ||
}}  | }}  | ||
Revision as of 00:12, 8 July 2017
Cache
- Main article: Skylake § Cache
 
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 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
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Memory controller
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 Integrated Memory Controller 
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Facts about "Core i7-6700HQ  - Intel"
| has ecc memory support | false + | 
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l2$ description | 4-way set associative + | 
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + | 
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + | 
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + | 
| max memory channels | 2 + | 
| supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |