Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i5/i5-6500te"
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{{mpu | {{mpu | ||
|name=Core i5-6500TE | |name=Core i5-6500TE | ||
| + | |image=skylake (fclga1151).png | ||
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=i5-6500TE | |model number=i5-6500TE | ||
|s-spec=SR2LR | |s-spec=SR2LR | ||
| + | |market=Embedded | ||
| + | |first announced=October 19, 2015 | ||
| + | |first launched=October 19, 2015 | ||
| + | |release price=$192.00 | ||
|family=Core i5 | |family=Core i5 | ||
|series=i5-6000 | |series=i5-6000 | ||
| Line 14: | Line 19: | ||
|turbo frequency3=3,100 MHz | |turbo frequency3=3,100 MHz | ||
|turbo frequency4=3,000 MHz | |turbo frequency4=3,000 MHz | ||
| + | |bus type=DMI 3.0 | ||
| + | |bus links=4 | ||
| + | |bus rate=8 GT/s | ||
| + | |clock multiplier=23 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
|microarch=Skylake | |microarch=Skylake | ||
| + | |chipset=Sunrise Point | ||
|core name=Skylake S | |core name=Skylake S | ||
|core family=6 | |core family=6 | ||
| + | |core model=94 | ||
|core stepping=R0 | |core stepping=R0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
| + | |die area=122 mm² | ||
|word size=64 bit | |word size=64 bit | ||
|core count=4 | |core count=4 | ||
|thread count=4 | |thread count=4 | ||
|max cpus=1 | |max cpus=1 | ||
| + | |max memory=64 GiB | ||
| + | |v core min=0.55 V | ||
| + | |v core max=1.52 V | ||
|tdp=35 W | |tdp=35 W | ||
| + | |tjunc min=0 °C | ||
| + | |tjunc max=100 °C | ||
| + | |tstorage min=-25 °C | ||
| + | |tstorage max=125 °C | ||
|package module 1={{packages/intel/fclga-1151}} | |package module 1={{packages/intel/fclga-1151}} | ||
}} | }} | ||
Revision as of 07:57, 8 July 2017
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i5-6500TE - Intel"
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |