From WikiChip
Difference between revisions of "intel/xeon e5/e5-2698 v4"
< intel‎ | xeon e5

(Benchmarks)
Line 193: Line 193:
 
{{benchmarks main
 
{{benchmarks main
 
|
 
|
{{benchmark entry
+
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q2/cpu2017-20161026-00026.html|test_timestamp=2016-12-09 16:58:22-0500|chip_count=2|core_count=40|copies_count=80|vendor=Inspur Corporation|system=Inspur NF5280M4 (Intel Xeon E5-2698 v4)|SPECrate2017_int_base=143|SPECrate2017_int_peak=148}}
|type=spec
+
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q2/cpu2017-20161026-00027.html|test_timestamp=2016-12-10 07:16:04-0500|chip_count=2|core_count=40|copies_count=80|vendor=Inspur Corporation|system=Inspur NF5280M4 (Intel Xeon E5-2698 v4)|SPECrate2017_fp_base=133|SPECrate2017_fp_peak=133}}
|test_link=https://www.spec.org/cpu2017/results/res2017q2/cpu2017-20161026-00027.html
 
|test_timestamp=2016-12-10 07:16:04-0500
 
|vendor=Inspur
 
|system=Inspur NF5280M4 (Intel Xeon E5-2698 v4)
 
|SPECrate2017_fp_base=133
 
|SPECrate2017_fp_peak=133
 
}}
 
{{benchmark entry
 
|type=spec
 
|test_link=https://www.spec.org/cpu2017/results/res2017q2/cpu2017-20161026-00026.html
 
|test_timestamp=2016-12-09 16:58:22-0500
 
|vendor=Inspur
 
|system=Inspur NF5280M4 (Intel Xeon E5-2698 v4)
 
|SPECrate2017_int_base=143
 
|SPECrate2017_int_peak=148
 
}}
 
 
}}
 
}}

Revision as of 02:16, 26 November 2017

Template:mpu The Xeon E5-2698 v4 is a 64-bit icosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 640 KiB
655,360 B
0.625 MiB
20x32 KiB 8-way set associative (per core, write-back)
L1D$ 640 KiB
655,360 B
0.625 MiB
20x32 KiB 8-way set associative (per core, write-back)
L2$ 5 MiB
5,120 KiB
5,242,880 B
0.00488 GiB
20x256 KiB 8-way set associative (per core, write-back)
L3$ 50 MiB
51,200 KiB
52,428,800 B
0.0488 GiB
20x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

Template:mpu expansions

Features

Template:mpu features

Benchmarks

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2016-12-09 16:58:22-0500
Chips: 2, Cores: 40, Copies: 80
benchmarks.svg
Vendor: Inspur Corporation
System: Inspur NF5280M4 (Intel Xeon E5-2698 v4)
SPECrate2017_int_base: 143
SPECrate2017_int_peak: 148
Test: SPEC CPU2017
Tested: 2016-12-10 07:16:04-0500
Chips: 2, Cores: 40, Copies: 80
benchmarks.svg
Vendor: Inspur Corporation
System: Inspur NF5280M4 (Intel Xeon E5-2698 v4)
SPECrate2017_fp_base: 133
SPECrate2017_fp_peak: 133
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-2698 v4 - Intel + and Xeon E5-2698 v4 - Intel +
l1d$ description8-way set associative +
l1d$ size640 KiB (655,360 B, 0.625 MiB) +
l1i$ description8-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description8-way set associative +
l2$ size5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) +
l3$ description20-way set associative +
l3$ size50 MiB (51,200 KiB, 52,428,800 B, 0.0488 GiB) +