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Difference between revisions of "intel/xeon e5/e5-2697 v4"
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== Features ==  
 
== Features ==  
{{mpu features
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{{x86 features
 
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| nx          = Yes
 
| nx          = Yes

Revision as of 14:48, 13 December 2017

Template:mpu The Xeon E5-2697 v4 is a 64-bit octadeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.3 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 576 KiB
589,824 B
0.563 MiB
18x32 KiB 8-way set associative (per core, write-back)
L1D$ 576 KiB
589,824 B
0.563 MiB
18x32 KiB 8-way set associative (per core, write-back)
L2$ 4.5 MiB
4,608 KiB
4,718,592 B
0.00439 GiB
18x256 KiB 8-way set associative (per core, write-back)
L3$ 45 MiB
46,080 KiB
47,185,920 B
0.0439 GiB
18x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

Template:mpu expansions

Features

has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size576 KiB (589,824 B, 0.563 MiB) +
l1i$ description8-way set associative +
l1i$ size576 KiB (589,824 B, 0.563 MiB) +
l2$ description8-way set associative +
l2$ size4.5 MiB (4,608 KiB, 4,718,592 B, 0.00439 GiB) +
l3$ description20-way set associative +
l3$ size45 MiB (46,080 KiB, 47,185,920 B, 0.0439 GiB) +