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Difference between revisions of "intel/core i3/i3-6100u"
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{{intel title|Core i3-6100U}}
 
{{intel title|Core i3-6100U}}
 
{{mpu
 
{{mpu
−
| name               = Intel Core i3-6100U
+
|name=Core i3-6100U
−
| no image           = Yes
+
|no image=Yes
−
| image               =
+
|image=skylake (bga1356).png
−
| image size          =
+
|designer=Intel
−
| caption            =  
+
|manufacturer=Intel
−
| designer           = Intel
+
|model number=i3-6100U
−
| manufacturer       = Intel
+
|part number=FJ8066201931104
−
| model number       = i3-6100U
+
|s-spec=SR2EU
−
| part number         = FJ8066201931104
+
|market=Mobile
−
| part number 2      =
+
|first announced=October 12, 2015
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| part number 3      =
+
|first launched=October 12, 2015
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| part number 4      =
+
|family=Core i3
−
| part number 5      =  
+
|series=i3-6000
−
| market             = Mobile
+
|locked=Yes
−
| first announced     = October 12, 2015
+
|frequency=2,300 MHz
−
| first launched     = October 12, 2015
+
|bus type=OPI
−
| last order          =
+
|bus rate=4 GT/s
−
| last shipment      =
+
|clock multiplier=23
−
 
+
|isa=x86-64
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| family             = Core i3
+
|isa family=x86
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| series             = 6100
+
|microarch=Skylake
−
| locked             = Yes
+
|core name=Skylake U
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| frequency         = 2300 MHz
+
|core family=6
−
| turbo frequency    =
+
|core model=78
−
| turbo frequency1  =
+
|core stepping=D1
−
| turbo frequency2  =
+
|process=14 nm
−
| turbo frequency3  =
+
|transistors=1,750,000,000
−
| turbo frequency4  =
+
|technology=CMOS
−
| bus type           =  
+
|die area=98.57 mm²
−
| bus speed          =  
+
|die length=10.3 mm
−
| clock multiplier   = 23
+
|die width=9.57 mm
−
| s-spec            = SR2EU
+
|mcp=Yes
−
 
+
|die count=2
−
| isa family         = x86
+
|word size=64 bit
−
| isa                = x86-64
+
|core count=2
−
| microarch          = Skylake  
+
|thread count=4
−
| platform          =  
+
|max cpus=1
−
| core name          = Skylake U
+
|max memory=32 GiB
−
| core stepping     = D1
+
|tdp=15 W
−
| process           = 14 nm
+
|ctdp down=7.5 W
−
| die size          =  
+
|ctdp down frequency=800 MHz
−
| word size         = 64 bits
+
|temp min=0 °C
−
| core count         = 2
+
|temp max=100 °C
−
| thread count       = 4
+
|tjunc min=0 °C
−
| max cpus           = 1
+
|tjunc max=100 °C
−
| max memory         = 32 GiB
+
|tstorage min=-25 °C
−
 
+
|tstorage max=125 °C
−
 
 
−
| sdp                =
 
−
| tdp                 = 15 W
 
−
| ctdp down           = 7.5 W
 
−
| ctdp down frequency = 800 MHz
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp max           = 100 °C
 
−
| temp min           = 0 °C
 
−
 
 
 
|package module 1={{packages/intel/fcbga-1356}}
 
|package module 1={{packages/intel/fcbga-1356}}
 
}}
 
}}

Revision as of 17:38, 3 July 2017

Template:mpu Core i3-6100U is a 64-bit dual-core low-end mobile performance microprocessor introduced by Intel late 2015. This processor, which is based on the Skylake microarchitecture and manufactured in 14 nm process, has a base frequency of 2.3 GHz with a TDP of 15 W with a configurable TDP-down of 7.5 W operating at 800 MHz. This processor incorporates the HD Graphics 520 GPU clocked at 300 MHz with a max frequency of 1 GHz.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 4-way set associative (per core, write-back)
L3$ 3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
shared

Graphics

Integrated Graphic Information
GPU Intel HD Graphics 520
Device ID 0x1916
Displays 3
Frequency 300 MHz
0.3 GHz
300,000 KHz
Max frequency 1 GHz
1,000 MHz
1,000,000 KHz
Max memory 32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Output DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX 12
OpenGL 4.4
OpenCL 2.0
HDMI 1.4a
DP 1.2
eDP 1.3
Max HDMI Res 4096x2304 @24 Hz
Max DP Res 4096x2304 @60 Hz
Max eDP Res 4096x2304 @60 Hz
Intel Quick Sync Video
Intel InTru 3D
Intel Insider
Intel WiDi (Wireless Display)
Intel Clear Video

Memory controller

Integrated Memory Controller
Type LPDDR3-1600, LPDDR3-1866, DDR4-1866, DDR4-2133
Controllers 1
Channels 2
ECC Support No
Max bandwidth 34,100 MB/s
Max memory 32,768 MB

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-6100u&oldid=50084"
Facts about "Core i3-6100U - Intel"
RDF feed
device id0x1916 +
has featureintegrated gpu +
integrated gpuIntel HD Graphics 520 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency1,000 MHz (1 GHz, 1,000,000 KHz) +
integrated gpu max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ descriptionshared +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +