Line 62: | Line 62: | ||
|l3 break=4x8 MiB | |l3 break=4x8 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM). Note that despite AMD's support for memory rates of 3,200 MT/s and possibly higher, rates beyond 2666 MT/s exceeds the [[JEDEC]] specification and is thus considered overclocking which voids AMD product warranty and likely any vendor or retailer warranties as well. | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=128 GiB | ||
+ | |controllers=4 | ||
+ | |channels=4 | ||
+ | |max bandwidth=79.47 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | This processor includes 60 PCIe lanes with PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16). | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 60 | ||
+ | | pcie config = x16 | ||
+ | | pcie config 2 = x8 | ||
+ | | pcie config 3 = x4 | ||
+ | | pcie config 4 = x1 | ||
+ | }} | ||
+ | * eMMC, LPC, SMBus, SPI/eSPI | ||
+ | |||
+ | == Audio == | ||
+ | Support Azalia High Definition Audio | ||
+ | |||
+ | == Graphics == | ||
+ | This processor has no integrated graphics. | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=Yes | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=Yes | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=No | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=Yes | ||
+ | |amdv=Yes | ||
+ | |rvi=No | ||
+ | |smt=Yes | ||
+ | |sensemi=Yes | ||
+ | |xfr=Yes | ||
}} | }} |
Revision as of 01:57, 27 June 2017
Template:mpu Ryzen Threadripper 1950X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor set to be introduced by AMD in mid-2017. The 1950X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1950X operates at a base frequency of 3.4 GHz with a TDP of 155 W. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM). Note that despite AMD's support for memory rates of 3,200 MT/s and possibly higher, rates beyond 2666 MT/s exceeds the JEDEC specification and is thus considered overclocking which voids AMD product warranty and likely any vendor or retailer warranties as well.
Integrated Memory Controller
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Expansions
This processor includes 60 PCIe lanes with PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16).
Expansion Options
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- eMMC, LPC, SMBus, SPI/eSPI
Audio
Support Azalia High Definition Audio
Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen Threadripper 1950X - AMD#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd extended frequency range | true + |
has amd sensemi technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Extended Frequency Range + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
max pcie lanes | 60 + |
supported memory type | DDR4-2666 + |