| Line 62: | Line 62: | ||
|l3 break=4x8 MiB | |l3 break=4x8 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
| + | }} | ||
| + | |||
| + | == Memory controller == | ||
| + | This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM). Note that despite AMD's support for memory rates of 3,200 MT/s and possibly higher, rates beyond 2666 MT/s exceeds the [[JEDEC]] specification and is thus considered overclocking which voids AMD product warranty and likely any vendor or retailer warranties as well. | ||
| + | {{memory controller | ||
| + | |type=DDR4-2666 | ||
| + | |ecc=Yes | ||
| + | |max mem=128 GiB | ||
| + | |controllers=4 | ||
| + | |channels=4 | ||
| + | |max bandwidth=79.47 GiB/s | ||
| + | |bandwidth schan=19.87 GiB/s | ||
| + | |bandwidth dchan=39.74 GiB/s | ||
| + | |bandwidth qchan=79.47 GiB/s | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | This processor includes 60 PCIe lanes with PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16). | ||
| + | {{expansions | ||
| + | | pcie revision = 3.0 | ||
| + | | pcie lanes = 60 | ||
| + | | pcie config = x16 | ||
| + | | pcie config 2 = x8 | ||
| + | | pcie config 3 = x4 | ||
| + | | pcie config 4 = x1 | ||
| + | }} | ||
| + | * eMMC, LPC, SMBus, SPI/eSPI | ||
| + | |||
| + | == Audio == | ||
| + | Support Azalia High Definition Audio | ||
| + | |||
| + | == Graphics == | ||
| + | This processor has no integrated graphics. | ||
| + | |||
| + | == Features == | ||
| + | {{x86 features | ||
| + | |real=Yes | ||
| + | |protected=Yes | ||
| + | |smm=Yes | ||
| + | |fpu=Yes | ||
| + | |x8616=Yes | ||
| + | |x8632=Yes | ||
| + | |x8664=Yes | ||
| + | |nx=Yes | ||
| + | |mmx=Yes | ||
| + | |emmx=Yes | ||
| + | |sse=Yes | ||
| + | |sse2=Yes | ||
| + | |sse3=Yes | ||
| + | |ssse3=Yes | ||
| + | |sse41=Yes | ||
| + | |sse42=Yes | ||
| + | |sse4a=Yes | ||
| + | |avx=Yes | ||
| + | |avx2=Yes | ||
| + | |avx512=No | ||
| + | |abm=Yes | ||
| + | |tbm=No | ||
| + | |bmi1=Yes | ||
| + | |bmi2=Yes | ||
| + | |fma3=Yes | ||
| + | |fma4=No | ||
| + | |aes=Yes | ||
| + | |rdrand=Yes | ||
| + | |sha=Yes | ||
| + | |xop=No | ||
| + | |adx=Yes | ||
| + | |clmul=Yes | ||
| + | |f16c=Yes | ||
| + | |tbt1=No | ||
| + | |tbt2=No | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=No | ||
| + | |sst=No | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |isrt=No | ||
| + | |sba=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=No | ||
| + | |txt=No | ||
| + | |ht=No | ||
| + | |vpro=No | ||
| + | |vtx=No | ||
| + | |vtd=No | ||
| + | |ept=No | ||
| + | |mpx=No | ||
| + | |sgx=No | ||
| + | |securekey=No | ||
| + | |osguard=No | ||
| + | |3dnow=No | ||
| + | |e3dnow=No | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdvi=Yes | ||
| + | |amdv=Yes | ||
| + | |rvi=No | ||
| + | |smt=Yes | ||
| + | |sensemi=Yes | ||
| + | |xfr=Yes | ||
}} | }} | ||
Revision as of 01:56, 27 June 2017
Template:mpu Ryzen Threadripper 1920X is a 64-bit dodeca-core high-performance x86 desktop microprocessor set to be introduced by AMD in mid-2017. The 1920X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1920X operates at a base frequency of 3.2 GHz with a TDP of 125 W and a Boost frequency of 3.8 GHz. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.
Cache
- Main article: Zen § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM). Note that despite AMD's support for memory rates of 3,200 MT/s and possibly higher, rates beyond 2666 MT/s exceeds the JEDEC specification and is thus considered overclocking which voids AMD product warranty and likely any vendor or retailer warranties as well.
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Integrated Memory Controller
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Expansions
This processor includes 60 PCIe lanes with PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16).
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Expansion Options
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- eMMC, LPC, SMBus, SPI/eSPI
Audio
Support Azalia High Definition Audio
Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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| l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |