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Difference between revisions of "amd/ryzen threadripper/1950x"
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'''Ryzen Threadripper 1950X''' is a {{arch|64}} [[hexadeca-core]] high-performance [[x86]] desktop [[microprocessor]] set to be introduced by [[AMD]] in mid-[[2017]]. The 1950X, which is based on their {{amd|Zen|Zen microarchitecture|l=arch}}, is fabricated on a [[14 nm process]]. The 1950X operates at a base frequency of 3.4 GHz with a [[TDP]] of 155 W. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory. | '''Ryzen Threadripper 1950X''' is a {{arch|64}} [[hexadeca-core]] high-performance [[x86]] desktop [[microprocessor]] set to be introduced by [[AMD]] in mid-[[2017]]. The 1950X, which is based on their {{amd|Zen|Zen microarchitecture|l=arch}}, is fabricated on a [[14 nm process]]. The 1950X operates at a base frequency of 3.4 GHz with a [[TDP]] of 155 W. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory. | ||
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+ | {{unknown features}} | ||
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+ | == Cache == | ||
+ | {{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1.5 MiB | ||
+ | |l1i cache=1 MiB | ||
+ | |l1i break=16x64 KiB | ||
+ | |l1i desc=4-way set associative | ||
+ | |l1d cache=512 KiB | ||
+ | |l1d break=16x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=8 MiB | ||
+ | |l2 break=16x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=32 MiB | ||
+ | |l3 break=4x8 MiB | ||
+ | |l3 desc=16-way set associative | ||
+ | }} |
Revision as of 02:36, 27 June 2017
Template:mpu Ryzen Threadripper 1950X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor set to be introduced by AMD in mid-2017. The 1950X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1950X operates at a base frequency of 3.4 GHz with a TDP of 155 W. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Ryzen Threadripper 1950X - AMD"
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |