From WikiChip
Difference between revisions of "intel/core m/m5-6y57"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
|||
Line 1: | Line 1: | ||
{{intel title|Core M5-6Y57}} | {{intel title|Core M5-6Y57}} | ||
{{mpu | {{mpu | ||
− | | name | + | |name=Core M5-6Y57 |
− | | | + | |image=skylake y (front).png |
− | + | |image size=250px | |
− | | image size | + | |designer=Intel |
− | + | |manufacturer=Intel | |
− | | designer | + | |model number=M5-6Y57 |
− | | manufacturer | + | |part number=HE8066201922876 |
− | | model number | + | |s-spec=SR2EG |
− | | part number | + | |market=Mobile |
− | | | + | |first launched=September 1, 2015 |
− | | | + | |release price=$281 |
− | | first launched | + | |family=Core M5 |
− | + | |series=6000 | |
− | + | |locked=Yes | |
− | | release price | + | |frequency=1100 MHz |
− | + | |turbo frequency1=2800 MHz | |
− | | family | + | |bus type=DMI 3.0 |
− | | series | + | |clock multiplier=11 |
− | | locked | + | |isa=x86-64 |
− | | frequency | + | |isa family=x86 |
− | + | |microarch=Skylake | |
− | | turbo frequency1 | + | |platform=Skylake |
− | + | |core name=Skylake Y | |
− | | bus type | + | |core family=6 |
− | + | |core model=78 | |
− | + | |core stepping=D1 | |
− | | clock multiplier | + | |process=14 nm |
− | | | + | |transistors=1,750,000,000 |
− | + | |technology=CMOS | |
− | + | |die area=98.57 mm² | |
− | + | |die length=10.3 mm | |
− | + | |die width=9.57 mm | |
− | | isa family | + | |mcp=Yes |
− | + | |die count=2 | |
− | | microarch | + | |word size=64 bit |
− | | platform | + | |core count=2 |
− | + | |thread count=4 | |
− | | core name | + | |max cpus=1 |
− | | core family | + | |max memory=16 GiB |
− | | core model | + | |sdp=3 W |
− | | core stepping | + | |tdp=4.5 W |
− | | process | + | |ctdp down=3.5 W |
− | | transistors | + | |ctdp down frequency=600 MHz |
− | | technology | + | |ctdp up=7 W |
− | | die area | + | |ctdp up frequency=1500 MHz |
− | | die width | + | |tjunc min=5 °C |
− | | die | + | |tjunc max=100 °C |
− | | word size | + | |package module 1={{packages/intel/fcbga-1515}} |
− | | core count | + | |turbo frequency=Yes |
− | | thread count | ||
− | | max cpus | ||
− | | max memory | ||
− | |||
− | |||
− | |||
− | |||
− | | sdp | ||
− | | tdp | ||
− | | ctdp down | ||
− | | ctdp down frequency = 600 MHz | ||
− | | ctdp up | ||
− | | ctdp up frequency | ||
− | | tjunc min | ||
− | | tjunc max | ||
− | |||
− | | package module 1 = {{packages/intel/fcbga-1515}} | ||
}} | }} | ||
'''Core M5-6Y57''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.8 GHz. This chip, which is manufactured on a [[14 nm process]], is based on the {{intel|Skylake}} microarchitecture. The Core M5-6Y57 incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz. | '''Core M5-6Y57''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.8 GHz. This chip, which is manufactured on a [[14 nm process]], is based on the {{intel|Skylake}} microarchitecture. The Core M5-6Y57 incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz. |
Revision as of 13:14, 3 July 2017
Template:mpu Core M5-6Y57 is an ultra-low power 64-bit dual-core x86 microprocessor introduced by Intel in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.8 GHz. This chip, which is manufactured on a 14 nm process, is based on the Skylake microarchitecture. The Core M5-6Y57 incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
Cache
- Main article: Skylake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||
|
Graphics
![]() |
Integrated Graphics Information
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features
[Edit/Modify Supported Features]
![]() |
Supported x86 Extensions & Processor Features
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Drivers
Facts about "Core m5-6Y57 - Intel"