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Difference between revisions of "intel/celeron/3955u"
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{{intel title|3955U}}
 
{{intel title|3955U}}
 
{{mpu
 
{{mpu
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| name               = Celeron 3955U
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|name=Celeron 3955U
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| no image           = Yes
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|no image=Yes
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| image             =
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|image=skylake (bga1356).png
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| image size        =
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|designer=Intel
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| caption            =  
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|manufacturer=Intel
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| designer           = Intel
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|model number=3955U
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| manufacturer       = Intel
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|s-spec=SR2EW
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| model number       = 3955U
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|market=Mobile
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| part number        =  
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|first announced=August 15, 2015
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| market             = Mobile
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|first launched=December 27, 2015
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| first announced   = August 15, 2015
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|family=Celeron
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| first launched     = December 27, 2015
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|series=3000
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| last order        =
+
|locked=Yes
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| last shipment      =
+
|frequency=2,000 MHz
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+
|bus type=OPI
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| family             = Celeron
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|bus rate=4 GT/s
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| series             = 3000
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|clock multiplier=20
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| locked             = Yes
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|isa=x86-64
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| frequency         = 2000 MHz
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|isa family=x86
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| turbo frequency    =  
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|microarch=Skylake
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| turbo frequency1  =  
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|core name=Skylake U
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| turbo frequency2  =  
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|core family=6
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| turbo frequency3  =  
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|core model=78
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| turbo frequency4  =  
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|core stepping=D1
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| bus type          =  
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|process=14 nm
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| bus speed          =  
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|transistors=1,750,000,000
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| clock multiplier  = 20
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|technology=CMOS
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| s-spec            =
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|die area=98.57 mm²
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+
|die length=10.3 mm
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| isa family          = x86
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|die width=9.57 mm
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| isa                = x86-64
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|mcp=Yes
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| microarch          = Skylake
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|die count=2
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| platform          =  
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|word size=64 bit
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| core name          = Skylake U
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|core count=2
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| core stepping      =  
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|thread count=2
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| process            = 14 nm
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|max cpus=1
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| die size          =  
+
|max memory=32 GiB
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| word size         = 64 bit
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|tdp=15 W
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| core count         = 2
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|ctdp down=10 W
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| thread count       = 2
+
|temp max=100 °C
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| max cpus           = 1
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|tjunc min=0 °C
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| max memory         = 32 GiB
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|tjunc max=100 °C
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|tstorage min=-25 °C
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|tstorage max=125 °C
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| tdp               = 15 W
 
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| ctdp down         = 10 W
 
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| ctdp up            =  
 
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| temp max           = 100 °C
 
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| temp min           =  
 
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|package module 1={{packages/intel/fcbga-1356}}
 
|package module 1={{packages/intel/fcbga-1356}}
 
}}
 
}}

Revision as of 16:38, 3 July 2017

Template:mpu The Intel Celeron 3955U is a dual-core 64-bit mobile microprocessor released by Intel in the third quarter of 2015. The 3955U is designed to replace the Broadwell-based celeron. Manufactured using 14nm process, the Skylake-based 3955U Celeron processor can be configured to run at down to 10 Watt TDP. This processor, just like its predecessor lack support for any of Intel's advanced technologies such as hyper-threading, trusted execution, transactional synchronization extensions (TSX), and turbo-boost.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 4-way set associative
L3$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB

Graphics

Integrated Graphic Information
GPU Intel HD Graphics 510
Displays 3
Frequency 300 MHz
0.3 GHz
300,000 KHz
Max frequency 900 MHz
0.9 GHz
900,000 KHz
Max memory 1700 MiB
1,740,800 KiB
1,782,579,200 B
1.66 GiB
Output DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX 12
OpenGL 4.4
Max HDMI Res 4096x2304 @24 Hz
Max DP Res 4096x2304 @60 Hz
Max eDP Res 4096x2304 @60 Hz

Memory controller

Integrated Memory Controller
Type DDR4-1866, DDR4-2133, LPDDR3-1600, LPDDR3-1866
Controllers 1
Channels 2
Max bandwidth 34,100 MB/s
Max memory 32,768 MB

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/3955u&oldid=50083"
Facts about "Celeron 3955U - Intel"
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has featureintegrated gpu +
integrated gpuIntel HD Graphics 510 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory1,700 MiB (1,740,800 KiB, 1,782,579,200 B, 1.66 GiB) +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +