Semiconductor & Computer Engineering
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Difference between revisions of "pezy/pezy-scx/pezy-sc3"
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|channels=8 | |channels=8 | ||
|max bandwidth=11.18 TiB/s | |max bandwidth=11.18 TiB/s | ||
| + | }} | ||
| + | |||
| + | |||
| + | == Expansions == | ||
| + | {{expansions | ||
| + | | pcie revision = 3.0 | ||
| + | | pcie lanes = 128 | ||
| + | | pcie config = x16 | ||
| + | | pcie config 2 = x8 | ||
| + | | pcie config 3 = x4 | ||
| + | | uart = Yes | ||
| + | | gp io = Yes | ||
}} | }} | ||
Revision as of 05:30, 23 June 2017
Template:mpu PEZY-SC3 (PEZY Super Computer 3) is fourth generation many-core microprocessor planned by PEZY. The SC3 incorporates 8,096 cores, four times as many cores as its predecessor.
Planned to be fabricated on TSMC's 7 nm process, PEZY-SC3 operates at 1.33 GHz and consume around 400 W while delivering performance in the order of 87.2 TFLOPS (HP), 43.6 TFLOPS (SP), and 21.8 TFLOPS (DP).
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Memory controller
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Integrated Memory Controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Facts about "PEZY-SC3 - PEZY"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SC3 - PEZY#io + |
| has ecc memory support | true + and false + |
| max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + and 11,448.32 GiB/s (11,723,079.68 MiB/s, 12,292.54 GB/s, 12,292,539.999 MB/s, 11.18 TiB/s, 12.293 TB/s) + |
| max memory channels | 4 + and 8 + |
| max pcie lanes | 128 + |
| supported memory type | DDR4-3600 + |