From WikiChip
Difference between revisions of "intel/xeon d/d-1518"
< intel‎ | xeon d

m (Bot: corrected mem)
m (Bot: corrected mem)
Line 103: Line 103:
 
| bandwidth schan    =  
 
| bandwidth schan    =  
 
| bandwidth dchan    =  
 
| bandwidth dchan    =  
−
| max memory        = 128 GB
+
| max memory        = 128 GiB
 
}}
 
}}
  

Revision as of 05:47, 23 June 2017

Template:mpu The Xeon D-1518 is a 64-bit quad-core x86-64 microserver SoC that was introduced by Intel in March of 2015. The D-1518 operates at 2 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 35 W and can support up to 128 GB of RAM (DDR3L/DDR4).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 8-way set associative (per core)
L3$ 6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
4x1.5 MiB (per core)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max memory 128 GiB

Expansions

Template:mpu expansions

Networking

Networking
SFI interface Yes
KR interface No
KX interface Yes
KX4 interface No
10Base-T No
100Base-T No
1000Base-T Yes
10GBase-T Yes

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-1518&oldid=46969"
Facts about "Xeon D-1518 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +