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    Difference between revisions of "cavium/octeon plus/cn5750-800bg1217-ssp"    
                	
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| model number        = CN5750-800 SSP  | | model number        = CN5750-800 SSP  | ||
| part number         = CN5750-800BG1217-SSP  | | part number         = CN5750-800BG1217-SSP  | ||
| − | |||
| part number 2       =    | | part number 2       =    | ||
| part number 3       =    | | part number 3       =    | ||
| + | | part number 4       =   | ||
| market              = Storage  | | market              = Storage  | ||
| first announced     = Jun 26, 2007  | | first announced     = Jun 26, 2007  | ||
Revision as of 17:08, 30 June 2017
Template:mpu CN5750-800 SSP is a 64-bit dodeca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
 
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 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
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Memory controller
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 Integrated Memory Controller 
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Expansions
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 Expansion Options 
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Networking
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
 - 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
 - 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
 
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 Networking 
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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 Hardware Accelerators 
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Block diagram
Datasheet
Facts about "CN5750-800 SSP  - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | CN5750-800 SSP - Cavium#io + | 
| has ecc memory support | true + | 
| has hardware accelerators for cryptography | true + | 
| has hardware accelerators for data compression | true + | 
| has hardware accelerators for data decompression | true + | 
| has hardware accelerators for network quality of service processing | true + | 
| has hardware accelerators for tcp packet processing | true + | 
| has hardware raid 5 support | true + | 
| has hardware raid 6 support | true + | 
| l1$ size | 576 KiB (589,824 B, 0.563 MiB) + | 
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + | 
| l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + | 
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + | 
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + | 
| max memory channels | 2 + | 
| max pcie lanes | 8 + | 
| supported memory type | DDR2-800 + |