From WikiChip
Difference between revisions of "amd/epyc/7601"
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|frequency=2,200 MHz | |frequency=2,200 MHz | ||
|turbo frequency1=3,200 MHz | |turbo frequency1=3,200 MHz | ||
+ | |turbo frequency2=3,200 MHz | ||
+ | |turbo frequency3=2,700 MHz | ||
+ | |turbo frequency4=2,700 MHz | ||
+ | |turbo frequency5=2,700 MHz | ||
+ | |turbo frequency6=2,700 MHz | ||
+ | |turbo frequency7=2,700 MHz | ||
+ | |turbo frequency8=2,700 MHz | ||
+ | |turbo frequency9=2,700 MHz | ||
+ | |turbo frequency10=2,700 MHz | ||
+ | |turbo frequency11=2,700 MHz | ||
+ | |turbo frequency12=2,700 MHz | ||
+ | |turbo frequency13=2,700 MHz | ||
+ | |turbo frequency14=2,700 MHz | ||
+ | |turbo frequency15=2,700 MHz | ||
+ | |turbo frequency16=2,700 MHz | ||
+ | |turbo frequency17=2,700 MHz | ||
+ | |turbo frequency18=2,700 MHz | ||
+ | |turbo frequency19=2,700 MHz | ||
+ | |turbo frequency20=2,700 MHz | ||
+ | |turbo frequency21=2,700 MHz | ||
+ | |turbo frequency22=2,700 MHz | ||
+ | |turbo frequency23=2,700 MHz | ||
+ | |turbo frequency24=2,700 MHz | ||
+ | |turbo frequency25=2,700 MHz | ||
+ | |turbo frequency26=2,700 MHz | ||
+ | |turbo frequency27=2,700 MHz | ||
+ | |turbo frequency28=2,700 MHz | ||
+ | |turbo frequency29=2,700 MHz | ||
+ | |turbo frequency30=2,700 MHz | ||
+ | |turbo frequency31=2,700 MHz | ||
+ | |turbo frequency32=2,700 MHz | ||
|bus links=4 | |bus links=4 | ||
|bus rate=8 GT/s | |bus rate=8 GT/s |
Revision as of 22:22, 20 June 2017
Template:mpu EPYC 7601 is a dual-socket 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7601 has a base frequency of 2.2 GHz with a turbo frequency of 3.2 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.
Contents
Cache
- Main article: Zen § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
The EPYC 7601 has 128 Gen 3 PCIe lanes.
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Expansion Options
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "EPYC 7601 - AMD"