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Difference between revisions of "amd/epyc/7551"
< amd‎ | epyc

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|frequency=2,000 MHz
 
|frequency=2,000 MHz
 
|turbo frequency1=3,000 MHz
 
|turbo frequency1=3,000 MHz
 +
|turbo frequency2=3,000 MHz
 +
|turbo frequency3=2,550 MHz
 +
|turbo frequency4=2,550 MHz
 +
|turbo frequency5=2,550 MHz
 +
|turbo frequency6=2,550 MHz
 +
|turbo frequency7=2,550 MHz
 +
|turbo frequency8=2,550 MHz
 +
|turbo frequency9=2,550 MHz
 +
|turbo frequency10=2,550 MHz
 +
|turbo frequency11=2,550 MHz
 +
|turbo frequency12=2,550 MHz
 +
|turbo frequency13=2,550 MHz
 +
|turbo frequency14=2,550 MHz
 +
|turbo frequency15=2,550 MHz
 +
|turbo frequency16=2,550 MHz
 +
|turbo frequency17=2,550 MHz
 +
|turbo frequency18=2,550 MHz
 +
|turbo frequency19=2,550 MHz
 +
|turbo frequency20=2,550 MHz
 +
|turbo frequency21=2,550 MHz
 +
|turbo frequency22=2,550 MHz
 +
|turbo frequency23=2,550 MHz
 +
|turbo frequency24=2,550 MHz
 +
|turbo frequency25=2,550 MHz
 +
|turbo frequency26=2,550 MHz
 +
|turbo frequency27=2,550 MHz
 +
|turbo frequency28=2,550 MHz
 +
|turbo frequency29=2,550 MHz
 +
|turbo frequency30=2,550 MHz
 +
|turbo frequency31=2,550 MHz
 +
|turbo frequency32=2,550 MHz
 
|bus links=4
 
|bus links=4
 
|bus rate=8 GT/s
 
|bus rate=8 GT/s
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|max cpus=2
 
|max cpus=2
 
|max memory=2 TiB
 
|max memory=2 TiB
−
|tdp=180W
+
|tdp=180 W
 
|package module 1={{packages/amd/socket sp3}}
 
|package module 1={{packages/amd/socket sp3}}
 
}}
 
}}

Revision as of 21:20, 20 June 2017

Template:mpu EPYC 7551 is a dual-socket 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7551 has a base frequency of 2 GHz with a turbo frequency of 3 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3 MiB
3,072 KiB
3,145,728 B
L1I$2 MiB
2,048 KiB
2,097,152 B
32x64 KiB4-way set associative 
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB8-way set associativewrite-back
L2$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  32x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  8x8 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem2 TiB
Controllers4
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

Expansions

The EPYC 7551 has 128 Gen 3 PCIe lanes.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes128
Configs8x16, 32x4


Features

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SenseMISenseMI Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7551&oldid=45437"
Facts about "EPYC 7551 - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7551 - AMD#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd sensemi technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ description8-way set associative +
l1d$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description4-way set associative +
l1i$ size2,048 KiB (2,097,152 B, 2 MiB) +
l2$ description8-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description16-way set associative +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels8 +
max pcie lanes128 +
supported memory typeDDR4-2666 +