Semiconductor & Computer Engineering
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Difference between revisions of "amd/epyc/7551p"
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Revision as of 18:20, 20 June 2017
Template:mpu EPYC 7551P is a 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7551P has a base frequency of 2 GHz with a turbo frequency of 3 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Zen § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "EPYC 7551P - AMD"
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has amd amd-v technology | true + |
| has amd amd-vi technology | true + |
| has amd sensemi technology | true + |
| has ecc memory support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
| max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
| max memory channels | 8 + |
| supported memory type | DDR4-2666 + |