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Difference between revisions of "amd/epyc/7551p"
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'''EPYC 7551P''' is a {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7551P has a base frequency of 2 GHz with a turbo frequency of 3 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory.
 
'''EPYC 7551P''' is a {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7551P has a base frequency of 2 GHz with a turbo frequency of 3 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory.
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{{unknown features}}
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== Cache ==
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
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{{cache size
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|l1 cache=1.5 MiB
 +
|l1i cache=1 MiB
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|l1i break=16x64 KiB
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|l1i desc=4-way set associative
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|l1d cache=512 KiB
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|l1d break=16x32 KiB
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|l1d desc=8-way set associative
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|l1d policy=write-back
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|l2 cache=8 MiB
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|l2 break=16x512 KiB
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|l2 desc=8-way set associative
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|l2 policy=write-back
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|l3 cache=64 MiB
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|l3 break=8x8 MiB
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|l3 desc=16-way set associative
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|l3 policy=write-back
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR4-2666
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|ecc=Yes
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|max mem=2 TiB
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|controllers=1
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|channels=8
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|max bandwidth=158.95 GiB/s
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|bandwidth schan=19.89 GiB/s
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|bandwidth dchan=39.72 GiB/s
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|bandwidth qchan=79.47 GiB/s
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|bandwidth hchan=119.21 GiB/s
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|bandwidth ochan=158.95 GiB/s
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}}
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== Features ==
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{{x86 features
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|real=Yes
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|protected=Yes
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|smm=Yes
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|fpu=Yes
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|x8616=Yes
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|x8632=Yes
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|x8664=Yes
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|nx=Yes
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|mmx=Yes
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|emmx=Yes
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|sse=Yes
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|sse2=Yes
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|sse3=Yes
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|ssse3=Yes
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|sse41=Yes
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|sse42=Yes
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|sse4a=Yes
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|avx=Yes
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|avx2=Yes
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|avx512=No
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|abm=Yes
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|tbm=No
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|bmi1=Yes
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|bmi2=Yes
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|fma3=Yes
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|fma4=No
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|aes=Yes
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|rdrand=Yes
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|sha=Yes
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|xop=No
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|adx=Yes
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|clmul=Yes
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|f16c=Yes
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|tbt1=No
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|tbt2=No
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|tbmt3=No
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|bpt=No
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|eist=No
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|sst=No
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|flex=No
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|fastmem=No
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|isrt=No
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|sba=No
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|mwt=No
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|sipp=No
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|att=No
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|ipt=No
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|tsx=No
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|txt=No
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|ht=No
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|vpro=No
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|vtx=No
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|vtd=No
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|ept=No
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|mpx=No
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|sgx=No
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|securekey=No
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|osguard=No
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|3dnow=No
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|e3dnow=No
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|smartmp=No
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|powernow=No
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|amdvi=Yes
 +
|amdv=Yes
 +
|rvi=No
 +
|smt=Yes
 +
|sensemi=Yes
 +
|xfr=No
 +
}}

Revision as of 18:18, 20 June 2017

Template:mpu EPYC 7551P is a 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7551P has a base frequency of 2 GHz with a turbo frequency of 3 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$1 MiB
1,024 KiB
1,048,576 B
16x64 KiB4-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  16x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  8x8 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem2 TiB
Controllers1
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SenseMISenseMI Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7551p&oldid=45268"
Facts about "EPYC 7551P - AMD"
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has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd sensemi technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description4-way set associative +
l1i$ size1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels8 +
supported memory typeDDR4-2666 +