From WikiChip
Difference between revisions of "intel/xeon gold/6138t"
< intel‎ | xeon gold

Line 1: Line 1:
 
{{intel title|Xeon Gold 6138T}}
 
{{intel title|Xeon Gold 6138T}}
 
{{mpu
 
{{mpu
| future             = Yes
+
|future=Yes
| name               = Xeon Gold 6138T
+
|name=Xeon Gold 6138T
| no image           = Yes
+
|no image=Yes
| image              =
+
|designer=Intel
| image size          =
+
|manufacturer=Intel
| caption            =
+
|model number=6138T
| designer           = Intel
+
|part number=CD8067303592900
| manufacturer       = Intel
+
|s-spec=SR3J7
| model number       = 6138T
+
|market=Server
| part number         = CD8067303592900
+
|first announced=April 25, 2017
| part number 1      =
+
|family=Xeon Gold
| part number 2      =
+
|series=6100
| s-spec             = SR3J7
+
|locked=Yes
| s-spec 2            =
+
|frequency=2.0 GHz
| market             = Server
+
|bus type=DMI 3.0
| first announced     = April 25, 2017
+
|bus links=4
| first launched      =
+
|bus rate=8 GT/s
| last order          =
+
|clock multiplier=20
| last shipment      =
+
|isa=x86-64
| release price      =
+
|isa family=x86
 
+
|microarch=Skylake
| family             = Xeon Gold
+
|platform=Purley
| series             = 6100
+
|chipset=Lewisburg
| locked             = Yes
+
|core name=Skylake SP
| frequency           = 2.0 GHz
+
|core family=6
| turbo frequency    =
+
|core stepping=H0
| turbo frequency1    =
+
|process=14 nm
| turbo frequency2    =
+
|technology=CMOS
| turbo frequency3    =
+
|die area=<!-- XX mm² -->
| turbo frequency4    =
+
|word size=64 bit
| turbo frequency5    =
+
|max cpus=4
| turbo frequency6    =
+
|v core tolerance=<!-- OR ... -->
| turbo frequency7    =
+
|v io 2=<!-- OR ... -->
| turbo frequency8    =
+
|temp min=<!-- use TJ/TC whenever possible instead -->
| bus type           = DMI 3.0
+
|tjunc min=<!-- .. °C -->
| bus speed          =  
+
|package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
| bus rate           = 8 GT/s
+
|packaging=Yes
| bus links          = 4
+
|package 0=FCLGA-3647
| clock multiplier   = 20
+
|package 0 type=LGA
| cpuid              =
+
|package 0 pins=3647
| cpuid 2            =
+
|socket 0=LGA-3647
 
+
|socket 0 type=LGA
| isa family          = x86
 
| isa                 = x86-64
 
| microarch           = Skylake
 
| platform           = Purley
 
| chipset             = Lewisburg
 
| core name           = Skylake SP
 
| core family         =
 
| core model          =  
 
| core stepping       = H0
 
| process             = 14 nm
 
| transistors        =
 
| technology         = CMOS
 
| die area           = <!-- XX mm² -->
 
| die width          =
 
| die length          =
 
| word size           = 64 bit
 
| core count          =
 
| thread count        =
 
| max cpus           = 4
 
| max memory          =
 
 
 
| electrical          =
 
| power              =
 
| average power      =
 
| idle power          =
 
| v core              =
 
| v core tolerance   = <!-- OR ... -->
 
| v core min          =
 
| v core max          =
 
| v io                =
 
| v io tolerance      =
 
| v io 2             = <!-- OR ... -->
 
| v io 3              =
 
| sdp                =
 
| tdp                =
 
| tdp typical        =
 
| ctdp down          =
 
| ctdp down frequency =
 
| ctdp up            =
 
| ctdp up frequency  =
 
| temp min           = <!-- use TJ/TC whenever possible instead -->
 
| temp max            =
 
| tjunc min           = <!-- .. °C -->
 
| tjunc max          =
 
| tcase min          =
 
| tcase max          =
 
| tstorage min        =
 
| tstorage max        =
 
| tambient min        =
 
| tambient max        =
 
 
 
| package module 1    =
 
| package module 2   =  
 
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
 
| packaging           = Yes
 
| package 0           = FCLGA-3647
 
| package 0 type     = LGA
 
| package 0 pins     = 3647
 
| package 0 pitch    =
 
| package 0 width    =
 
| package 0 length    =
 
| package 0 height    =
 
| socket 0           = LGA-3647
 
| socket 0 type       = LGA
 
 
}}
 
}}
 
'''Xeon Gold 6138T''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6138T operates at 2.0 GHz
 
'''Xeon Gold 6138T''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6138T operates at 2.0 GHz

Revision as of 23:57, 29 June 2017

Template:mpu Xeon Gold 6138T is a 64-bit x86 high-performance server multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6138T operates at 2.0 GHz


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
EISTEnhanced SpeedStep Technology
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
SMEPOS Guard Technology
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard +
has intel enhanced speedstep technologytrue +
has intel supervisor mode execution protectiontrue +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
x86/has memory protection extensionstrue +