Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
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-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 cpp Δ|}}} || {{{process 6 cpp Δ|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 cpp Δ|}}} || {{{process 6 cpp Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 mmp|}}} || {{{process 1 mmp Δ|}}} || {{{process 2 mmp|}}} || {{{process 2 mmp Δ|}}} || {{{process 3 mmp|}}} || {{{process 3 mmp Δ|}}} | + | | {{{process 1 mmp|}}} || {{{process 1 mmp Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 mmp Δ|}}} || {{{process 2 mmp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 mmp Δ|}}} || {{{process 3 mmp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 mmp Δ|}}} || {{{process 4 mmp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 mmp Δ|}}} || {{{process 5 mmp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 mmp Δ|}}} || {{{process 6 mmp Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 sram hp|}}} || {{{process 1 sram hp Δ|}}} || {{{process 2 sram hp|}}} || {{{process 2 sram hp Δ|}}} || {{{process 3 sram hp|}}} || {{{process 3 sram hp Δ|}}} | + | | {{{process 1 sram hp|}}} || {{{process 1 sram hp Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 sram hp Δ|}}} || {{{process 2 sram hp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 sram hp Δ|}}} || {{{process 3 sram hp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 sram hp Δ|}}} || {{{process 4 sram hp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 sram hp Δ|}}} || {{{process 5 sram hp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 sram hp Δ|}}} || {{{process 6 sram hp Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 sram hd|}}} || {{{process 1 sram hd Δ|}}} || {{{process 2 sram hd|}}} || {{{process 2 sram hd Δ|}}} || {{{process 3 sram hd|}}} || {{{process 3 sram hd Δ|}}} | + | | {{{process 1 sram hd|}}} || {{{process 1 sram hd Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 sram hd Δ|}}} || {{{process 2 sram hd Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 sram hd Δ|}}} || {{{process 3 sram hd Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 sram hd Δ|}}} || {{{process 4 sram hd Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 sram hd Δ|}}} || {{{process 5 sram hd Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 sram hd Δ|}}} || {{{process 6 sram hd Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 sram lv|}}} || {{{process 1 sram lv Δ|}}} || {{{process 2 sram lv|}}} || {{{process 2 sram lv Δ|}}} || {{{process 3 sram lv|}}} || {{{process 3 sram lv Δ|}}} | + | | {{{process 1 sram lv|}}} || {{{process 1 sram lv Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 sram lv Δ|}}} || {{{process 2 sram lv Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 sram lv Δ|}}} || {{{process 3 sram lv Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 sram lv Δ|}}} || {{{process 4 sram lv Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 sram lv Δ|}}} || {{{process 5 sram lv Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 sram lv Δ|}}} || {{{process 6 sram lv Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 dram|}}} || {{{process 1 dram Δ|}}} || {{{process 2 dram|}}} || {{{process 2 dram Δ|}}} || {{{process 3 dram|}}} || {{{process 3 dram Δ|}}} | + | | {{{process 1 dram|}}} || {{{process 1 dram Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 dram Δ|}}} || {{{process 2 dram Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 dram Δ|}}} || {{{process 3 dram Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 dram Δ|}}} || {{{process 4 dram Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 dram Δ|}}} || {{{process 5 dram Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 dram Δ|}}} || {{{process 6 dram Δ|}}} }} | ||
|} | |} | ||
</div> | </div> | ||
Revision as of 03:36, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | |
|---|---|