Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "Template:finfet nodes comp"
| Line 31: | Line 31: | ||
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 lith|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 lith|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | colspan="2" | {{{process 1 immersion|}}} || colspan="2" | {{{process 2 immersion|}}} || colspan="2" | {{{process | + | | colspan="2" | {{{process 1 immersion|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 immersion|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | colspan="2" | {{{process 1 exposure|}}} || colspan="2" | {{{process 2 exposure|}}} || colspan="2" | {{{process | + | | colspan="2" | {{{process 1 exposure|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 exposure|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 exposure|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 exposure|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 exposure|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 exposure|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | colspan="2" | {{{process 1 wafer type|}}} || colspan="2" | {{{process 2 wafer type|}}} || colspan="2" | {{{process | + | | colspan="2" | {{{process 1 wafer type|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 wafer type|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 wafer type|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 wafer type|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 wafer type|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 wafer type|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | colspan="2" | {{{process 1 wafer size|}}} || colspan="2" | {{{process 2 wafer size|}}} || colspan="2" | {{{process | + | | colspan="2" | {{{process 1 wafer size|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 wafer size|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 wafer size|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 wafer size|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 wafer size|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 wafer size|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | colspan="2" | {{{process 1 transistor|}}} || colspan="2" | {{{process 2 transistor|}}} || colspan="2" | {{{process | + | | colspan="2" | {{{process 1 transistor|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 transistor|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 transistor|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 transistor|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 transistor|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 transistor|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | colspan="2" | {{{process 1 volt|}}} || colspan="2" | {{{process 2 volt|}}} || colspan="2" | {{{process | + | | colspan="2" | {{{process 1 volt|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 volt|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 volt|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 volt|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 volt|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 volt|}}} }} | ||
|- | |- | ||
! Value !! {{{process 1 delta from|}}} !! Value !! {{{process 2 delta from|}}} !! Value !! {{{process 3 delta from|}}} | ! Value !! {{{process 1 delta from|}}} !! Value !! {{{process 2 delta from|}}} !! Value !! {{{process 3 delta from|}}} | ||
Revision as of 03:08, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | Value | Value | |||
|---|---|---|---|---|---|