Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
| Line 8: | Line 8: | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="2" | {{{process 1 date|}}} || colspan="2" | {{{process 2 date|}}} || colspan="2" | {{{process 3 date|}}} | | colspan="2" | {{{process 1 date|}}} || colspan="2" | {{{process 2 date|}}} || colspan="2" | {{{process 3 date|}}} | ||
| + | |- style="text-align: center;" | ||
| + | | colspan="2" | {{{process 1 lith|}}} || colspan="2" | {{{process 2 lith|}}} || colspan="2" | {{{process 3 lith|}}} | ||
| + | |- style="text-align: center;" | ||
| + | | colspan="2" | {{{process 1 immersion|}}} || colspan="2" | {{{process 2 immersion|}}} || colspan="2" | {{{process 3 immersion|}}} | ||
| + | |- style="text-align: center;" | ||
| + | | colspan="2" | {{{process 1 exposure|}}} || colspan="2" | {{{process 2 exposure|}}} || colspan="2" | {{{process 3 exposure|}}} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="2" | {{{process 1 wafer type|}}} || colspan="2" | {{{process 2 wafer type|}}} || colspan="2" | {{{process 3 wafer type|}}} | | colspan="2" | {{{process 1 wafer type|}}} || colspan="2" | {{{process 2 wafer type|}}} || colspan="2" | {{{process 3 wafer type|}}} | ||
Revision as of 00:23, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | Value | Value | |||
|---|---|---|---|---|---|