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Difference between revisions of "cavium/octeon plus/cn5740-800bg1217-ssp"
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'''CN5740-800 SSP''' is a {{arch|64}} [[octa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration.
 
'''CN5740-800 SSP''' is a {{arch|64}} [[octa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration.

Revision as of 00:25, 23 June 2017

Template:mpu CN5740-800 SSP is a 64-bit octa-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
8x16 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels2
Width64 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision1.0
Max Lanes8
Configsx4, x8
UART
GP I/OYes


Networking

Interface options:

  • 8-lanes PCIe + 8-lanes PCIe
  • 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
  • 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
XAUIYes (Ports: 1)
SGMIIYes (Ports: 4)

Hardware Accelerators

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
Types3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes
RAID
RAID 5Yes
RAID 6Yes

Block diagram

cn57xx block diagram.png

Datasheet

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5740-800bg1217-ssp&oldid=46353"
Facts about "CN5740-800 SSP - Cavium"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5740-800 SSP - Cavium#package + and CN5740-800 SSP - Cavium#io +
base frequency800 MHz (0.8 GHz, 800,000 kHz) +
core count8 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5740-800bg1217-ssp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5740-800 SSP +
nameCavium CN5740-800 SSP +
packageFCBGA-1217 +
part numberCN5740-800BG1217-SSP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +