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'''CN5745-900 SSP''' is a {{arch|64}} [[deca-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates ten {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration. | '''CN5745-900 SSP''' is a {{arch|64}} [[deca-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates ten {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=480 KiB | ||
+ | |l1i cache=320 KiB | ||
+ | |l1i break=10x32 KiB | ||
+ | |l1d cache=160 KiB | ||
+ | |l1d break=10x16 KiB | ||
+ | |l2 cache=2 MiB | ||
+ | |l2 break=1x2 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-800 | ||
+ | |ecc=Yes | ||
+ | |max mem= | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |width=64 bit | ||
+ | |max bandwidth=11.92 GiB/s | ||
+ | |bandwidth schan=5.96 GiB/s | ||
+ | |bandwidth dchan=11.92 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pcie revision=1.0 | ||
+ | |pcie lanes=8 | ||
+ | |pcie config=x4 | ||
+ | |pcie config 2=x8 | ||
+ | |uart=yes | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | Interface options: | ||
+ | * 8-lanes [[PCIe]] + 8-lanes PCIe | ||
+ | * 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI] | ||
+ | * 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI] | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |sgmii=yes | ||
+ | |sgmii ports=4 | ||
+ | |xaui=1 | ||
+ | |xaui ports=1 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH | ||
+ | |compression=Yes | ||
+ | |decompression=Yes | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | |raid=Yes | ||
+ | |raid5=Yes | ||
+ | |raid6=Yes | ||
+ | }} | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:cn57xx block diagram.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:CN57XX PB Rev 1.2.pdf|OCTEON CN57XX Processors Product Brief]] |
Revision as of 13:29, 29 December 2016
Template:mpu CN5745-900 SSP is a 64-bit deca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Networking
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN5745-900 SSP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5745-900 SSP - Cavium#io + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
has hardware raid 5 support | true + |
has hardware raid 6 support | true + |
l1$ size | 480 KiB (491,520 B, 0.469 MiB) + |
l1d$ size | 160 KiB (163,840 B, 0.156 MiB) + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 8 + |
supported memory type | DDR2-800 + |