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    Difference between revisions of "cavium/octeon plus/cn5740-900bg1217-sp"    
                	
														|  (Created page with "{{cavium title|CN5740-900 SP}} {{mpu | name                = Cavium CN5740-900 SP | no image            =  | image               = Octeon CN57xx.svg | image size          =  |...") | |||
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| | package 0 pins      = 1217 | | package 0 pins      = 1217 | ||
| | package 0 pitch     =   | | package 0 pitch     =   | ||
| − | | package 0 width     =   | + | | package 0 width     = 40 mm | 
| − | | package 0 length    =   | + | | package 0 length    = 40 mm | 
| | package 0 height    =   | | package 0 height    =   | ||
| | socket 0            = BGA-1217 | | socket 0            = BGA-1217 | ||
| | socket 0 type       = BGA | | socket 0 type       = BGA | ||
| }} | }} | ||
| + | '''CN5740-900 SP''' is a {{arch|64}} [[octa-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration. | ||
Revision as of 01:25, 29 December 2016
Template:mpu CN5740-900 SP is a 64-bit octa-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 900 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Facts about "CN5740-900 SP  - Cavium"
