Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon plus/cn5850-1000bg1521-exp"
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| family = OCTEON Plus | | family = OCTEON Plus | ||
| series = CN58xx | | series = CN58xx | ||
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| locked = | | locked = | ||
| frequency = 1,000 MHz | | frequency = 1,000 MHz | ||
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| socket 0 type = BGA | | socket 0 type = BGA | ||
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| + | '''CN5850-1000 EXP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration. | ||
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|spi42=Yes | |spi42=Yes | ||
|spi42 ports=2 | |spi42 ports=2 | ||
| + | }} | ||
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| + | == Hardware Accelerators == | ||
| + | {{accelerators | ||
| + | |regex=Yes | ||
| + | |regex feature=32 Engines | ||
| + | |compression=Yes | ||
| + | |decompression=Yes | ||
| + | |tcp=Yes | ||
| + | |qos=Yes | ||
}} | }} | ||
Revision as of 22:42, 15 December 2016
Template:mpu CN5850-1000 EXP is a 64-bit dodeca-core MIPS network microprocessor designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as RegEx, compression/decompression, and TCP acceleration.
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Facts about "CN5850-1000 EXP - Cavium"
