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Difference between revisions of "cavium/octeon plus/cn5830-900bg1521-nsp"
< cavium‎ | octeon plus

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|l2 break=1x2 MiB
 
|l2 break=1x2 MiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR2-800
 +
|ecc=Yes
 +
|max mem=
 +
|controllers=1
 +
|channels=1
 +
|width=128 bit
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 
}}
 
}}
  

Revision as of 02:12, 15 December 2016

Template:mpu


Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB64-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
4x16 KiB64-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2
GP I/OYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)
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Facts about "CN5830-900 NSP - Cavium"
RDF feed
has ecc memory supporttrue +
l1$ size192 KiB (196,608 B, 0.188 MiB) +
l1d$ description64-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description64-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
supported memory typeDDR2-800 +