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Difference between revisions of "cavium/octeon/cn3850-600bg1521-nsp"
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The '''CN3850-600 NSP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
 
The '''CN3850-600 NSP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Revision as of 21:43, 22 June 2017

Template:mpu The CN3850-600 NSP is a 64-bit dodeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$480 KiB
491,520 B
0.469 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB64-way set associative 
L1D$96 KiB
98,304 B
0.0938 MiB
12x8 KiB64-way set associativeWrite-through
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Max Mem16 GiB
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2
GP I/OYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
RegEx
RegExYes
Features16 Engines
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes

Block diagram

octeon cn38xx block diagram.png

Datasheet

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3850-600bg1521-nsp&oldid=46222"
Facts about "CN3850-600 NSP - Cavium"
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CN3850-600 NSP - Cavium#package +
base frequency600 MHz (0.6 GHz, 600,000 kHz) +
core count12 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedSeptember 13, 2004 +
first launchedJune 1, 2005 +
full page namecavium/octeon/cn3850-600bg1521-nsp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size480 KiB (491,520 B, 0.469 MiB) +
l1d$ description64-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description64-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateJune 1, 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3850-600 NSP +
nameCavium CN3850-600 NSP +
packageFCBGA-1521 +
part numberCN3850-600BG1521-NSP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3800 +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count12 +
word size64 bit (8 octets, 16 nibbles) +