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Difference between revisions of "cavium/octeon/cn3850-500bg1521-nsp"
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The '''CN3850-500 NSP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Revision as of 20:00, 10 December 2016

Template:mpu The CN3850-500 NSP is a 64-bit dodeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

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Facts about "CN3850-500 NSP - Cavium"
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CN3850-500 NSP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count12 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedSeptember 13, 2004 +
first launchedJune 1, 2005 +
full page namecavium/octeon/cn3850-500bg1521-nsp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size480 KiB (491,520 B, 0.469 MiB) +
l1d$ description64-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description64-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateJune 1, 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3850-500 NSP +
nameCavium CN3850-500 NSP +
packageFCBGA-1521 +
part numberCN3850-500BG1521-NSP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3800 +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count12 +
word size64 bit (8 octets, 16 nibbles) +