Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon/cn3630-500bg1521-nsp"
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| + | The '''CN3630-500 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz and dissipates 22 Watts. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | ||
Revision as of 04:57, 10 December 2016
Template:mpu The CN3630-500 NSP is a 64-bit quad-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 500 MHz and dissipates 22 Watts. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.