From WikiChip
Difference between revisions of "cavium/octeon/cn3120-300bg868-scp"
(→Features) |
|||
Line 157: | Line 157: | ||
}} | }} | ||
− | == | + | == Hardware Accelerators == |
− | + | {{accelerators | |
− | + | |encryption=Yes | |
− | + | |encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH | |
− | + | |tcp=Yes | |
− | + | |qos=Yes | |
+ | }} | ||
== Block diagram == | == Block diagram == |
Revision as of 17:11, 10 December 2016
Template:mpu The CN3120-300 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 300 MHz and dissipates 3 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||||
|
Optional low-latency controller for content-based processing and meta data
![]() |
Integrated Memory Controller
|
|||||||||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||||||||||||||||||
|
Networking
![]() |
Networking
|
|||||||
|
Hardware Accelerators
[Edit/Modify Accelerators Info]
![]() |
Hardware Accelerators
|
|||||||||||
|
Block diagram
Datasheet
Facts about "CN3120-300 SCP - Cavium"
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-667 + |