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Difference between revisions of "cavium/octeon/cn3120-500bg868-nsp"
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The '''CN3120-500 NSP''' is a {{arch|64}} [[dual-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a two {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network services such as [[encryption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
 
The '''CN3120-500 NSP''' is a {{arch|64}} [[dual-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a two {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network services such as [[encryption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
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== Cache ==
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{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
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{{cache size
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|l1 cache=80 KiB
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|l1i cache=64 KiB
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|l1i break=2x32 KiB
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|l1i desc=4-way set associative
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|l1d cache=16 KiB
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|l1d break=2x8 KiB
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|l1d desc=64-way set associative
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|l1d policy=Write-through
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|l2 cache=256 KiB
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|l2 break=1x128 KiB
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|l2 desc=8-way set associative
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}}

Revision as of 03:42, 9 December 2016

Template:mpu The CN3120-500 NSP is a 64-bit dual-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a two cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$80 KiB
81,920 B
0.0781 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
2x8 KiB64-way set associativeWrite-through
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x128 KiB8-way set associative 
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Facts about "CN3120-500 NSP - Cavium"
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l1$ size80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description64-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +