Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon/cn3110-500bg868-cp"
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| + | The '''CN3110-500 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a {{cavium|cnMIPS|l=arch}} core, operates at 500. This processor includes a number of hardware accelerators for network processing such as high-performance I/O packet processing, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | ||
Revision as of 02:32, 9 December 2016
Template:mpu The CN3110-500 SCP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a cnMIPS core, operates at 500. This processor includes a number of hardware accelerators for network processing such as high-performance I/O packet processing, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.