From WikiChip
Difference between revisions of "cavium/octeon/cn3005-500bg350-cp"
< cavium‎ | octeon

(Created page with "{{cavium title|CN3005 500 MHz CP}} {{mpu | name = Cavium CN3005-500 CP | no image = cn3005-15.png | image = | image size = |...")
 
Line 45: Line 45:
 
| die width          =  
 
| die width          =  
 
| die length          =  
 
| die length          =  
−
| word size          =  
+
| word size          = 64 bit
−
| core count          =  
+
| core count          = 1
−
| thread count        =  
+
| thread count        = 1
−
| max cpus            =  
+
| max cpus            = 1
 
| max memory          = 2 GiB
 
| max memory          = 2 GiB
 
| max memory addr    =  
 
| max memory addr    =  

Revision as of 05:24, 8 December 2016

Template:mpu The CN3005-500 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2005. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration.

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3005-500bg350-cp&oldid=30619"