From WikiChip
Difference between revisions of "mediatek/helio/mt6757"
< mediatek‎ | helio

Line 88: Line 88:
 
}}
 
}}
 
'''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in [[2017]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports dual-channel LPDDR4-1600. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900  MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6.
 
'''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in [[2017]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports dual-channel LPDDR4-1600. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900  MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6.
 +
 +
 +
 +
{{unknown features}}
 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}}
 +
{{cache size
 +
|l1 cache = 512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=2-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=2 MiB
 +
|l2 break=2x1 MiB
 +
|l2 desc=16-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR3-933
 +
|type 2=LPDDR4-1600
 +
|ecc=No
 +
|max mem=4 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=23.84 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 +
|bandwidth dchan=23.84 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
|usb revision=2.0
 +
|usb revision 2=3.0
 +
|usb ports=8
 +
|uart=4
 +
|gp io=Yes
 +
}}
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Mali-T880
 +
| device id          =
 +
| designer            = ARM Holdings
 +
| execution units    = 2
 +
| max displays        = 2
 +
| max memory          =
 +
| frequency          = 900 MHz
 +
 +
| output dsi          = Yes
 +
 +
| max res dsi        = 1920x1080
 +
 +
| direct3d ver        = 11.2
 +
| opencl ver          = 1.2
 +
| opengl ver          = 3.2
 +
| opengl es ver      = 3.2
 +
| vulkan ver          = 1.0
 +
| openvg ver          = 1.1
 +
}}
 +
 +
== Wireless ==
 +
{{wireless links
 +
| 2g                = Yes
 +
| csd              = Yes
 +
| gsm              = Yes
 +
| gprs              = Yes
 +
| edge              = Yes
 +
| cdmaone          =
 +
| is-95a            =
 +
| is-95b            =
 +
| 3g                = Yes
 +
| cdma2000          =
 +
| cdma2000 1x      =
 +
| cdma2000 1xev-do  =
 +
| cdma2000 1x adv  =
 +
| umts              = Yes
 +
| wcdma            = 
 +
| td-scdma          = Yes
 +
| dc-hsdpa          = Yes
 +
| hsdpa            =
 +
| hsupa            = Yes
 +
| 4g                = Yes
 +
| lte a            = Yes
 +
| e-utran          = Yes
 +
| ue cat            = 6
 +
}}

Revision as of 21:10, 5 December 2016

Template:mpu Helio P20 (MT6757) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and set to be launched in 2017. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 16 nm process, operates at up to 2.3 GHz and supports dual-channel LPDDR4-1600. This chip incorporates the Mali-T880 IGP operating at 900 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 6.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB4-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-933, LPDDR4-1600
Supports ECCNo
Max Mem4 GiB
Controllers1
Channels2
Max Bandwidth23.84 GiB/s
24,412.16 MiB/s
25.598 GB/s
25,598.005 MB/s
0.0233 TiB/s
0.0256 TB/s
Bandwidth
Single 11.92 GiB/s
Double 23.84 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0, 3.0
Ports8
UART
GP I/OYes


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-T880
DesignerARM Holdings
Execution Units2Max Displays2
Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDSI
Max Resolution
DSI1920x1080
Standards
Direct3D11.2
OpenGL3.2
OpenCL1.2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
2G
CSD Yes
GSM Yes
GPRS Yes
EDGE Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
4G
LTE Advanced
E-UTRANYes
UE Cat6
Retrieved from "https://en.wikichip.org/w/index.php?title=mediatek/helio/mt6757&oldid=30488"
Facts about "Helio P20 (MT6757) - MediaTek"
RDF feed
has 2g supporttrue +
has 3g supporttrue +
has 4g supporttrue +
has csd supporttrue +
has dc-hsdpa supporttrue +
has e-utran supporttrue +
has ecc memory supportfalse +
has edge supporttrue +
has gprs supporttrue +
has gsm supporttrue +
has hsupa supporttrue +
has lte advanced supporttrue +
has td-scdma supporttrue +
has umts supporttrue +
integrated gpuMali-T880 +
integrated gpu base frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units2 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) +
max memory channels2 +
supported memory typeLPDDR3-933 + and LPDDR4-1600 +
user equipment category6 +