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Difference between revisions of "intel/core i7/i7-5500du"
< intel‎ | core i7

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|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 
|l3 extra=(shared)
 
|l3 extra=(shared)
 +
}}
 +
 +
== Graphics ==
 +
No information about the [[integrated graphics processor]] is available.
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR3L-1866
 +
| type 2            = LPDDR4-2133
 +
| controllers        = 1
 +
| channels          = 2
 +
| ecc support        = Yes
 +
| max bandwidth      = 31.79 GiB/s
 +
| bandwidth schan    = 15.89 GiB/s
 +
| bandwidth dchan    = 31.79 GiB/s
 +
| max memory        = 32 GiB
 +
| pae                =
 +
}}
 +
 +
==Expansions==
 +
{{mpu expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 12
 +
| pcie config        = 1x4
 +
| pcie config 1      = 2x2
 +
| pcie config 2      = 1x2+2x1 and 4x1
 +
| usb revision      =
 +
| usb revision 2    =
 +
| usb revision N    =
 +
| usb ports          =
 +
| sata ports        =
 +
| integrated lan    =
 +
| uart              =
 +
}}
 +
 +
== Features ==
 +
{{mpu features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        =
 +
| vpro        =
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4        = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        = Yes
 +
| sgx        = Yes
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 
}}
 
}}

Revision as of 12:18, 24 November 2016

Template:mpu Core i7-5500DU is a 64-bit dual-core x86 performance mobile microprocessor introduced by Intel in early 2016. This processor operates at 2.4 GHz and is based on the Broadwell microarchitecture manufactured on a 14 nm process.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 4-way set associative (per core, write-back)
L3$ 4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
2x2 MiB 16-way set associative (shared)

Graphics

No information about the integrated graphics processor is available.

Memory controller

Integrated Memory Controller
Type DDR3L-1866, LPDDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max bandwidth 31.79 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 32 GiB

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i7/i7-5500du&oldid=28988"
Facts about "Core i7-5500DU - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description16-way set associative +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +