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Difference between revisions of "intel/xeon e7/e7-4830"
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{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
 
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
 
{{cache info
 
{{cache info
−
|l1i cache=256 KB
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|l1i cache=256 KiB
−
|l1i break=8x32 KB
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|l1i break=8x32 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
−
|l1d cache=256 KB
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|l1d cache=256 KiB
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|l1d break=8x32 KB
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|l1d break=8x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
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|l2 cache=2 MB
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|l2 cache=2 MiB
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|l2 break=8x256 KB
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|l2 break=8x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core)
 
|l2 extra=(per core)

Revision as of 23:50, 20 September 2016

Template:mpu Xeon E7-4830 is a 64-bit octa-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2.13 GHz with turob frequency of 2.4 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.

Cache

Main article: Westmere § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 4-way set associative (per core)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8x256 KiB 8-way set associative (per core)
L3$ 24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3-800, DDR3-978, DDR3-1066
Controllers 1
Channels 4
ECC Support Yes
Max memory 2048 GB

Features

Template:mpu features

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l1d$ description8-way set associative +
l1i$ description4-way set associative +
l2$ description8-way set associative +
l3$ description16-way set associative +