Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6/amd-k6/300afr"
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | {{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | ||
| − | [[L2$]] can be 256 | + | [[L2$]] can be 256 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip. |
{{cache info | {{cache info | ||
| − | |l1i cache=32 | + | |l1i cache=32 KiB |
| − | |l1i break=1x32 | + | |l1i break=1x32 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=32 | + | |l1d cache=32 KiB |
| − | |l1d break=1x32 | + | |l1d break=1x32 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
Revision as of 23:18, 20 September 2016
Template:mpu AMD-K6/300AFR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1998. This chip, which was based on AMD's new K6 microarchitecture, operated at 300 MHz and dissipated a maximum of 15.4 W.
Cache
- Main article: K6 § Cache
L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
Gallery
300AFR, Week 34, 1998
300AFR, Week 14, 1998
Documents
DataSheet
- AMD-K6 Processor Data Sheet; Publication #20695 Revision H/0; March 1998
Facts about "AMD-K6/300AFR - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |