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Difference between revisions of "amd/am8086/md8086"
(→Cache) |
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Line 76: | Line 76: | ||
{{main|intel/microarchitectures/8086#Memory_Hierarchy|l1=8086 § Cache}} | {{main|intel/microarchitectures/8086#Memory_Hierarchy|l1=8086 § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1 cache=0 | + | |l1 cache=0 KiB |
− | |l1 break=1x0 | + | |l1 break=1x0 KiB |
|l1 desc= | |l1 desc= | ||
|l1 extra= | |l1 extra= |
Revision as of 23:01, 20 September 2016
Template:mpu MD8086 is a second-sourced 8086 designed by Intel and manufactured by AMD in a 40-pin Ceramic DIP. This chip operated at 5 MHz. This model is rated for military use (Approved Product List, Class B) and is fully MIL-STD-883C compliant.
Cache
- Main article: 8086 § Cache
Cache Info [Edit Values] | ||
L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
Features
- Military grade
- ISA-compatible with 8080
- Direct addressing up to 1 MB
- 16-bit arithmetic