-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "amd/am286/n80286-10"
(→Cache) |
|||
Line 77: | Line 77: | ||
{{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}} | {{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1 cache=0 | + | |l1 cache=0 KiB |
− | |l1 break=1x0 | + | |l1 break=1x0 KiB |
|l1 desc= | |l1 desc= | ||
|l1 extra= | |l1 extra= | ||
− | |l2 cache=0 | + | |l2 cache=0 KiB |
− | |l2 break=1x0 | + | |l2 break=1x0 KiB |
}} | }} | ||
Revision as of 22:52, 20 September 2016
Template:mpu N80286-10 was an member of AMD's Am286 family designed by Intel and manufactured by AMD. This MPU was rated to operate at 10 MHz and was packaged in a 68-pin Plastic Leadless Chip Carrier package.
Cache
- Main article: 80286 § Cache
Cache Info [Edit Values] | ||
L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
L2$ | 0 KiB 0 MiB 0 B 0 GiB |
1x0 KiB |
Graphics
This chip had no integrated graphics processing unit.
Features
- Protected mode
- Supports FPU coprocessor (Am287)