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Difference between revisions of "intel/core i3/6120t"
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|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(per core, write-back) | |l2 extra=(per core, write-back) | ||
| − | |l3 cache=3 | + | |l3 cache=3 MiB |
|l3 desc=shared | |l3 desc=shared | ||
}} | }} | ||
Revision as of 00:51, 19 September 2016
Template:mpu
Core i3-6120T is a 64-bit dual-core low-end performance microprocessor set to be introduced by Intel in 2016.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L1D$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L2$ | 512 KB "KB" is not declared as a valid unit of measurement for this property. |
2x256 KB 4-way set associative (per core, write-back) |
| L3$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB |
shared |
Expansions
Features
Facts about "Core i3-6120T - Intel"
| l1d$ description | 8-way set associative + |
| l1i$ description | 8-way set associative + |
| l2$ description | 4-way set associative + |
| l3$ description | shared + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |