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Difference between revisions of "intel/core i3/6120t"
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| + | == Cache == | ||
| + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
| + | {{cache info | ||
| + | |l1i cache=64 KB | ||
| + | |l1i break=2x32 KB | ||
| + | |l1i desc=8-way set associative | ||
| + | |l1i extra=(per core, write-back) | ||
| + | |l1d cache=64 KB | ||
| + | |l1d break=2x32 KB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d extra=(per core, write-back) | ||
| + | |l2 cache=512 KB | ||
| + | |l2 break=2x256 KB | ||
| + | |l2 desc=4-way set associative | ||
| + | |l2 extra=(per core, write-back) | ||
| + | |l3 cache=3 MB | ||
| + | |l3 desc=shared | ||
| + | }} | ||
Revision as of 03:06, 13 May 2016
Template:mpu
Core i3-6120T is a 64-bit dual-core low-end microprocessor set to be introduced by Intel in 2016.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L1D$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L2$ | 512 KB "KB" is not declared as a valid unit of measurement for this property. |
2x256 KB 4-way set associative (per core, write-back) |
| L3$ | 3 MB "MB" is not declared as a valid unit of measurement for this property. |
shared |
Facts about "Core i3-6120T - Intel"
| l1d$ description | 8-way set associative + |
| l1i$ description | 8-way set associative + |
| l2$ description | 4-way set associative + |
| l3$ description | shared + |