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Difference between revisions of "intel/mcs-8/isa"
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The '''8008 ISA''' (or ''MCS-8 ISA'') was an instruction set architecture used in the {{intel|mcs-8/8008|8008}} and {{intel|mcs-8/8008-1|8008-1}} microprocessors.
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The '''8008 ISA''' (or ''MCS-8 ISA'') was an instruction set architecture introduced by [[Intel]] in 1972 and was used in the {{intel|mcs-8/8008|8008}} and {{intel|mcs-8/8008-1|8008-1}} microprocessors.
  
 
This ISA has an {{arch|8}} data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.
 
This ISA has an {{arch|8}} data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.
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== ISA ==
 
== ISA ==
 
Data on the 8008 is always stored in an 8-bit binary integer.
 
Data on the 8008 is always stored in an 8-bit binary integer.
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: <div style="text-align: center; width: 150px;">Data Word<div style="border: 1px solid black;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div></div>
+
: <div style="text-align: center; width: 175px;">Data Word<div style="border: 1px solid black;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div></div>
  
 
Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:
 
Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:
  
−
: <div style="text-align: center; width: 150px;">1-Byte Inst<div style="border: 1px solid black;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 140px;">OPCode</div></div>
+
: <div style="text-align: center; width: 175px;">1-Byte Inst<div style="border: 1px solid black;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 165;">OPCode</div></div>
  
 
Instructions that involve an [[immediate value]] have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.
 
Instructions that involve an [[immediate value]] have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.
  
−
:<div style="text-align: center; width: 310px;"><div style="width: 300px;">2-Byte Inst</div><div style="border: 1px solid black; width: 150px; float: left;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 150px; float: right;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 150px; float: left;">OPCode</div><div style="width: 150px; float: right;">Imm Value</div></div>
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:<div style="text-align: center; width: 360px;"><div style="width: 350px;">2-Byte Inst</div><div style="border: 1px solid black; width: 175px; float: left;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 175px; float: right;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 175px; float: left;">OPCode</div><div style="width: 175px; float: right;">Imm Value</div></div>
  
 
Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are [[don't care]]s.
 
Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are [[don't care]]s.
  
−
:<div style="text-align: center; width: 470px;"><div style="width: 470px;">3-Byte Inst</div><div style="border: 1px solid black; width: 150px; float: left;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 150px; float: right;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 150px; margin:0 auto;width:150px;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 150px; float: left;">OPCode</div><div style="width: 150px; float: right;">High-Order Add</div><div style="width: 150px; margin:0 auto;">Low-Order Add</div></div>
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:<div style="text-align: center; width: 550px;"><div style="width: 525px;">3-Byte Inst</div><div style="border: 1px solid black; width: 175px; float: left;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 175px; float: right;">{{X}}<sub>7</sub> {{X}}<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 175px; margin:0 auto;width:175px;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 175px; float: left;">OPCode</div><div style="width: 175px; float: right;">High-Order Addrs</div><div style="width: 175px; margin:0 auto;">Low-Order Addrs</div></div>
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=== Listing ===
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The 8008 ISA has 48 instructions broken a number of groups:
 +
 
 +
* [[#index_register|Index Register Instructions]]
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* [[#accumulator_group|Accumulator Group Instructions]]
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* [[#pc_and_stack|Program Counter and Stack Control Instructions]]
 +
* [[#io|Input/Output Instructions]]
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* [[#machine|Machine Instructions]]
 +
 
 +
In 1972, Intel introduce their first set of mnemonics for their instructions. This original set consists of three characters which meant it could easily be encoded into a lookup table. A few years later, when they released their {{intel|8080}} and its instruction set, they also revamped the 8008 mnemonics to match the 8080's ones more closely. The newer mnemonics resemble a primitive version of modern x86 mnemonics. Since 8008 programs can be found using bother mnemonics, both the "old" and the "new" mnemonics are listed below. Both mnemonics results in identical binary values.
 +
 
 +
{{isa
 +
| title    = 8008 ISA
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| mn title = Mnemonic (old)
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| col 1    = Mnemonic (new)
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| listing  =
 +
 
 +
{{inst|cols=4|section=<span id="index_register">'''Index Register Instructions'''</span><br><small>Load instructions do not affect any flag. The Inc and Dec instructions affect all flags except carry.</small>}}
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{{inst|mn=LR<sub>d</sub>R<sub>s</sub>  |col 1=MOV R<sub>d</sub>, R<sub>s</sub> |op={{bin|11 DDD SSS}} |act=R<sub>d</sub> = R<sub>s</sub>}}
 +
{{inst|mn=LR<sub>d</sub>M  |col 1=MOV R<sub>d</sub>, M |op={{bin|11 DDD 111}} |act=R<sub>d</sub> = Mem}}
 +
{{inst|mn=LMR<sub>s</sub>  |col 1=MOV R<sub>s</sub>, M |op={{bin|11 111 SSS}} |act=Mem = R<sub>s</sub>}}
 +
{{inst|mn=LR<sub>d</sub>I  |col 1=MVI R<sub>d</sub>, Imm |op={{bin|00 DDD 110}} {{bin|BB BBB BBB}} |act=R<sub>d</sub> = B<sub>7</sub>...B<sub>0</sub>}}
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{{inst|mn=LMI  |col 1=MVI M, Imm |op={{bin|00 111 110}} {{bin|BB BBB BBB}} |act=Mem = B<sub>7</sub>...B<sub>0</sub>}}
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{{inst|mn=INR<sub>d</sub>  |col 1=INR R<sub>d</sub> |op={{bin|00 DDD 000}} |act=R<sub>d</sub> = R<sub>d</sub> + 1 ({{l|neq|R<sub>d</sub>|A}})}}
 +
{{inst|mn=DCR<sub>d</sub>  |col 1=DCR R<sub>d</sub> |op={{bin|00 DDD 001}} |act=R<sub>d</sub> = R<sub>d</sub> - 1 ({{l|neq|R<sub>d</sub>|A}})}}
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 +
{{inst|cols=4|section=<span id="accumulator_group">'''Accumulator Group Instructions'''</span><br><small>The result of an ALU instruction affect all flags. The rotation instructions only affect the carry flag.</small>}}
 +
 
 +
{{inst|cols=4|section=<span id="pc_and_stack">'''Program Counter and Stack Control Instructions'''</span>}}
 +
 
 +
{{inst|cols=4|section=<span id="io">'''Input/Output Instructions'''</span>}}
 +
{{inst|cols=4|section=<span id="machine">'''Machine Instructions'''</span>}}
 +
}}
  
 
== See also ==
 
== See also ==
 
* {{intel|MCS-8}}
 
* {{intel|MCS-8}}
 
* {{intel|MCS-4}}
 
* {{intel|MCS-4}}

Revision as of 03:16, 26 March 2016

8008 ISA
Developer Intel
Datapoint Corporation
Implementation 8008
Dev model proprietary
Design Von Neumann architecture
Data word size 8 bit
1 octets
2 nibbles
Instruction word size 8 bit
1 octets
Instructions 48
Introduction 1972
Version 1
Format register-register
Endianness bi-endian
Registers 0
GPRs 7 (scratchpad)
ISAs • By Company • By Inst • By Data

The 8008 ISA (or MCS-8 ISA) was an instruction set architecture introduced by Intel in 1972 and was used in the 8008 and 8008-1 microprocessors.

This ISA has an 8-bit data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.

Registers

The 8008 had seven scratchpad registers. A few of them had additional capabilities - A is used an an accumulator register. Registers H & L are high-order and low-order words of a 14-bit address.

Register Size Purpose
A 8 bit Accumulator
B 8 bit GP
C 8 bit GP
D 8 bit GP
E 8 bit GP
H 8 bit High-order word
L 8 bit Low-order word

ISA

Data on the 8008 is always stored in an 8-bit binary integer.

Data Word
D7 D6 D5 D4 D3 D2 D1 D0

Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:

1-Byte Inst
D7 D6 D5 D4 D3 D2 D1 D0
OPCode

Instructions that involve an immediate value have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.

2-Byte Inst
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
OPCode
Imm Value

Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are don't cares.

3-Byte Inst
D7 D6 D5 D4 D3 D2 D1 D0
X7 X6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
OPCode
High-Order Addrs
Low-Order Addrs

Listing

The 8008 ISA has 48 instructions broken a number of groups:

In 1972, Intel introduce their first set of mnemonics for their instructions. This original set consists of three characters which meant it could easily be encoded into a lookup table. A few years later, when they released their 8080 and its instruction set, they also revamped the 8008 mnemonics to match the 8080's ones more closely. The newer mnemonics resemble a primitive version of modern x86 mnemonics. Since 8008 programs can be found using bother mnemonics, both the "old" and the "new" mnemonics are listed below. Both mnemonics results in identical binary values.

8008 ISA
Mnemonic (old)
Index Register Instructions
Load instructions do not affect any flag. The Inc and Dec instructions affect all flags except carry.
LRdRsMOV Rd, Rs11 DDD SSS2Rd = Rs
LRdMMOV Rd, M11 DDD 1112Rd = Mem
LMRsMOV Rs, M11 111 SSS2Mem = Rs
LRdIMVI Rd, Imm00 DDD 1102 BB BBB BBB2Rd = B7...B0
LMIMVI M, Imm00 111 1102 BB BBB BBB2Mem = B7...B0
INRdINR Rd00 DDD 0002Rd = Rd + 1 (Rd ≠ A)
DCRdDCR Rd00 DDD 0012Rd = Rd - 1 (Rd ≠ A)
Accumulator Group Instructions
The result of an ALU instruction affect all flags. The rotation instructions only affect the carry flag.
Program Counter and Stack Control Instructions
Input/Output Instructions
Machine Instructions

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/mcs-8/isa&oldid=15933"
Facts about "8008 ISA - Intel"
RDF feed
designerIntel + and Datapoint Corporation +
first launched1972 +
full page nameintel/mcs-8/isa +
implementation8008 - Intel +
instance ofinstruction set architecture +
instruction count48 +
instruction word size8 bit (1 octets) +
name8008 +
word size8 bit (1 octets, 2 nibbles) +