Semiconductor & Computer Engineering
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The MC14500B is a true {{arch|1}} microprocessor - all operations are done on single-bit operands. The MC14500B comes with an internal clock that may be controlled via an external resistor. While designed to run at 1 MHz, it may be tuned down to 10 KHz or hooked up to an external clock altogether. | The MC14500B is a true {{arch|1}} microprocessor - all operations are done on single-bit operands. The MC14500B comes with an internal clock that may be controlled via an external resistor. While designed to run at 1 MHz, it may be tuned down to 10 KHz or hooked up to an external clock altogether. | ||
| − | The MC14500B does not include any on-chip memory nor a [[program counter]]. A program counter is not provided because this MPU has no notion of memory at all, and by extension no notion of addresses. It implements an early [[Harvard architecture]] type of flow where separate instruction lines and data lines are fed to it. Individual instructions and values are fed in each clock cycle and the result can be read via a number of output lines. Typically a [[PROM]] chip such as the {{motorola|MCM7641}} and PC such as the {{motorola|MC145168}} | + | The MC14500B does not include any on-chip memory nor a [[program counter]]. A program counter is not provided because this MPU has no notion of memory at all, and by extension no notion of addresses. It implements an early [[Harvard architecture]] type of flow where separate instruction lines and data lines are fed to it. Individual instructions and values are fed in each clock cycle and the result can be read via a number of output lines. Typically a [[PROM]] chip such as the {{motorola|MCM7641}} and PC such as the {{motorola|MC145168}} were used to form a complete system. Because this was done externally, in theory at least, this MPU can support any amount of memory needed. |
The MC14500B has a number of output lines to help facilitate [[subroutine]] returns, [[branching]], [[conditional]], and general purpose I/O. How since there are no built-in support for memory or addressing, they have to be dealt with externally, possibly with some glue chips. | The MC14500B has a number of output lines to help facilitate [[subroutine]] returns, [[branching]], [[conditional]], and general purpose I/O. How since there are no built-in support for memory or addressing, they have to be dealt with externally, possibly with some glue chips. | ||
Revision as of 08:29, 21 January 2016
Template:mpu The Motorola MC14500B or Industrial Control Unit (ICU) is a 1-bit microprocessor designed by Motorola and released in 1976. Production continued well into the 1990s. The MC14500B was designed as an extremely low cost programmable logic controller suited for implementing various ladder logic circuits as replacement for older relay-based systems.
Architecture
The MC14500B is a true 1-bit microprocessor - all operations are done on single-bit operands. The MC14500B comes with an internal clock that may be controlled via an external resistor. While designed to run at 1 MHz, it may be tuned down to 10 KHz or hooked up to an external clock altogether.
The MC14500B does not include any on-chip memory nor a program counter. A program counter is not provided because this MPU has no notion of memory at all, and by extension no notion of addresses. It implements an early Harvard architecture type of flow where separate instruction lines and data lines are fed to it. Individual instructions and values are fed in each clock cycle and the result can be read via a number of output lines. Typically a PROM chip such as the MCM7641 and PC such as the MC145168 were used to form a complete system. Because this was done externally, in theory at least, this MPU can support any amount of memory needed.
The MC14500B has a number of output lines to help facilitate subroutine returns, branching, conditional, and general purpose I/O. How since there are no built-in support for memory or addressing, they have to be dealt with externally, possibly with some glue chips.
Registers
The MC14500B has a single register: result register (RR) which always stores the value of the intimidate operation that has been performed. RR can be read directly from pin 15 at any time. RR is also always used as the
Instruction Set
| Mnemonic | OPCode | Action |
|---|---|---|
| NOPO | 0x0 | RR → RR ; Flag O → 1 |
| LD | 0x1 | Data → RR |
| LDC | 0x2 | Data → RR |
| AND | 0x3 | RR · Data → RR |
| ANDC | 0x4 | RR · Data → RR |
| OR | 0x5 | RR + Data → RR |
| ORC | 0x6 | RR + Data → RR |
| XNOR | 0x7 | If RR = Data, RR → 1 |
| STO | 0x8 | RR → Data ; Write → 1 |
| STOC | 0x9 | RR → Data ; Write → 1 |
| IEN | 0xA | Data → IEN |
| OEN | 0xB | Data → OEN |
| JMP | 0xC | JMP Flag → 1 |
| RTN | 0xD | RTN Flag → 1 |
| SKZ | 0xE | Skip next instruction if RR = 0 |
| NOPF | 0xF | RR → RR ; Flag F → 1 |