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Difference between revisions of "20-bit architecture"

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The '''20-bit''' [[computer architecture]] is a [[microprocessor]] architecture that has a [[datapath]] width or a highest [[operand]] width of 20 bits or 2.5 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 20 bits.
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The '''20-bit [[architecture]]''' is a [[microprocessor]] or [[computer]] architecture that has a [[datapath]] width or a highest [[operand]] width of 20 bits or 2.5 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 20 bits.
  
  

Latest revision as of 00:02, 17 January 2016

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The 20-bit architecture is a microprocessor or computer architecture that has a datapath width or a highest operand width of 20 bits or 2.5 octets. These architectures typically have a matching register file with registers width of 20 bits.


20-bit microprocessors[edit]


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