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Difference between revisions of "mips/coprocessor 0"
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| − | '''Coprocessor 0''' (also known as the '''CP0''' or '''system control coprocessor''') is a required coprocessor part of the | + | {{mips title|Coprocessor 0}} |
| + | '''Coprocessor 0''' (also known as the '''CP0''' or '''system control coprocessor''') is a required [[coprocessor]] part of the {{mips|MIPS32}} and {{mips|MIPS64}} ISA which provides the facilities needed for an operating system. | ||
== Coprocessor 0 instructions == | == Coprocessor 0 instructions == | ||
| Line 7: | Line 8: | ||
! Mnemonic || Description | ! Mnemonic || Description | ||
|- | |- | ||
| − | | | + | | {{mips|MFC0}} || Move from Coprocessor 0 |
|- | |- | ||
| − | | | + | | {{mips|MTC0}} || Move to Coprocessor 0 |
|} | |} | ||
| Line 16: | Line 17: | ||
{| class="wikitable sortable" | {| class="wikitable sortable" | ||
| − | ! | + | ! Register Mnemonic || Register Number || Description |
|- | |- | ||
| [[Index register - MIPS|Context]] || 0 || rowspan="8" | memory management (TLB) | | [[Index register - MIPS|Context]] || 0 || rowspan="8" | memory management (TLB) | ||
Latest revision as of 09:11, 19 February 2018
Coprocessor 0 (also known as the CP0 or system control coprocessor) is a required coprocessor part of the MIPS32 and MIPS64 ISA which provides the facilities needed for an operating system.
Coprocessor 0 instructions[edit]
The following instructions can be used to read and write from CP0 registers.
| Mnemonic | Description |
|---|---|
| MFC0 | Move from Coprocessor 0 |
| MTC0 | Move to Coprocessor 0 |
Control Registers[edit]
| Register Mnemonic | Register Number | Description |
|---|---|---|
| Context | 0 | memory management (TLB) |
| Random | 1 | |
| EntryLo0 | 2 | |
| EntryLo1 | 3 | |
| Context | 4 | |
| PageMask | 5 | |
| Wired | 6 | |
| EntryHi | 10 | |
| HWREna | 7.0 | Sets user-privilege programs permissions |
| BadVAddr | 8 | Program address of the violation |
| Count | 9 | high-resolution time |
| Compare | 11 | |
| SR | 12 | Status Register |
| IntCtl | 12.1 | Interrupt vector setup |
| SRSCtl | 12.2 | Shadow register control |
| SRSMap | 12.3 | Shadow register map |
| Cause | 13 | Cause Register |
| EPC | 14 | Exception Program Counter |
| PRId | 15 | Product ID register |
| EBase | 15.1 | Exception entry point base address |
| Config | 16 | CPU setup |
| Config1 | 16.1 | |
| Config2 | 16.2 | |
| Config3 | 16.3 | |
| LLAddr | 17.0 | Cache address |
| Debug | 23.0 | EJTAG debug |
| DEPC | 24.0 | |
| DESAVE | 31.0 | |
| CacheErr | 27 | Memory error analysis registers |
| ECC | 26 | |
| ErrorEPC | 30 | |
| TagLo | 28 | Cache manipulation |
| DataLo | 28.1 | |
| TagHi | 29.0 | |
| DataHi | 29.1 | |
| WatchLo | 18.0 | Data watchpoint facility |
| WatchHi | 19.0 | |
| PerfCtl | 25.0 | Performance counter registers |
| PerfCnt | 25.1 |