From WikiChip
Difference between revisions of "intel/xeon e3/e3-1558l v5"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
(12 intermediate revisions by 2 users not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Xeon E3-1558L v5}} | {{intel title|Xeon E3-1558L v5}} | ||
− | {{ | + | {{chip |
|name=Xeon E3-1558L v5 | |name=Xeon E3-1558L v5 | ||
− | |image= | + | |no image=Yes |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
Line 48: | Line 48: | ||
|package module 1={{packages/intel/fcbga-1440}} | |package module 1={{packages/intel/fcbga-1440}} | ||
}} | }} | ||
− | '''Xeon E3-1558L v5''' is a {{arch|64}} [[quad-core]] [[x86]] mobile workstation microprocessor introduced by [[Intel]] in early | + | '''Xeon E3-1558L v5''' is a {{arch|64}} [[quad-core]] [[x86]] high-end performance mobile workstation [[microprocessor]] introduced by [[Intel]] in early 2016. The E3-1558L v5, which is based on the {{intel|Skylake|l=arch}} microarchitecture and is fabricated on a [[14 nm process]], has a base frequency of 1.9 GHz and a {{intel|turbo boost}} frequency of up to 3.3 GHz with a TDP of 45 W. This processor incorporates the {{intel|Iris Pro Graphics P555}} [[integrated graphics]] operating at 650 MHz with a turbo frequency of 1 GHz and incorporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory. |
+ | |||
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
Line 67: | Line 68: | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | |l4 cache=128 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=LPDDR3-1866 | ||
+ | |type 2=DDR3L-1600 | ||
+ | |type 3=DDR4-2133 | ||
+ | |ecc=Yes | ||
+ | |max mem=64 GiB | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |max bandwidth=31.79 GiB/s | ||
+ | |bandwidth schan=15.89 GiB/s | ||
+ | |bandwidth dchan=31.79 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 16 | ||
+ | | pcie config = 1x16 | ||
+ | | pcie config 2 = 2x8 | ||
+ | | pcie config 3 = 1x8+2x4 | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This integrated graphics includes an additional 128 MiB of eDRAM on-chip. | ||
+ | {{integrated graphics | ||
+ | | gpu = Iris Pro Graphics P555 | ||
+ | | device id = 0x192D | ||
+ | | designer = Intel | ||
+ | | execution units = 48 | ||
+ | | max displays = 3 | ||
+ | | max memory = 64 GiB | ||
+ | | frequency = 650 MHz | ||
+ | | max frequency = 1,000 MHz | ||
+ | |||
+ | | output crt = | ||
+ | | output sdvo = | ||
+ | | output dsi = | ||
+ | | output edp = Yes | ||
+ | | output dp = Yes | ||
+ | | output hdmi = Yes | ||
+ | | output vga = | ||
+ | | output dvi = Yes | ||
+ | |||
+ | | directx ver = 12 | ||
+ | | opengl ver = 4.4 | ||
+ | | opencl ver = 2.0 | ||
+ | | hdmi ver = 1.4a | ||
+ | | dp ver = 1.2 | ||
+ | | edp ver = 1.3 | ||
+ | | max res hdmi = 4096x2304 | ||
+ | | max res hdmi freq = 24 Hz | ||
+ | | max res dp = 4096x2304 | ||
+ | | max res dp freq = 60 Hz | ||
+ | | max res edp = 4096x2304 | ||
+ | | max res edp freq = 60 Hz | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
+ | |||
+ | | features = Yes | ||
+ | | intel quick sync = Yes | ||
+ | | intel intru 3d = Yes | ||
+ | | intel insider = | ||
+ | | intel widi = | ||
+ | | intel fdi = | ||
+ | | intel clear video = Yes | ||
+ | | intel clear video hd = Yes | ||
+ | }} | ||
+ | {{skylake hardware accelerated video table|col=1}} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=Yes | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
}} | }} |
Latest revision as of 15:27, 13 December 2017
Edit Values | |||||||||||||
Xeon E3-1558L v5 | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | E3-1558L v5 | ||||||||||||
S-Spec | SR2TU | ||||||||||||
Market | Embedded | ||||||||||||
Introduction | May 31, 2016 (announced) May 31, 2016 (launched) | ||||||||||||
Release Price | $396.00 | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Xeon E3 | ||||||||||||
Series | E3-1500 v5 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 1,900 MHz | ||||||||||||
Turbo Frequency | 3,300 MHz (1 core), 3,200 MHz (2 cores), 3,100 MHz (3 cores), 3,100 MHz (4 cores) | ||||||||||||
Bus type | DMI 3.0 | ||||||||||||
Bus rate | 4 × 8 GT/s | ||||||||||||
Clock multiplier | 19 | ||||||||||||
Microarchitecture | |||||||||||||
ISA | x86-64 (x86) | ||||||||||||
Microarchitecture | Skylake | ||||||||||||
Core Name | Skylake H | ||||||||||||
Core Family | 6 | ||||||||||||
Core Model | 94 | ||||||||||||
Core Stepping | N0 | ||||||||||||
Process | 14 nm | ||||||||||||
Technology | CMOS | ||||||||||||
MCP | Yes (2 dies) | ||||||||||||
Word Size | 64 bit | ||||||||||||
Cores | 4 | ||||||||||||
Threads | 8 | ||||||||||||
Max Memory | 64 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
Vcore | 0.55 V-1.52 V | ||||||||||||
TDP | 45 W | ||||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||||
Packaging | |||||||||||||
|
Xeon E3-1558L v5 is a 64-bit quad-core x86 high-end performance mobile workstation microprocessor introduced by Intel in early 2016. The E3-1558L v5, which is based on the Skylake microarchitecture and is fabricated on a 14 nm process, has a base frequency of 1.9 GHz and a turbo boost frequency of up to 3.3 GHz with a TDP of 45 W. This processor incorporates the Iris Pro Graphics P555 integrated graphics operating at 650 MHz with a turbo frequency of 1 GHz and incorporating 128 MiB of eDRAM on-package. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Expansions[edit]
Expansion Options
|
||||||||
|
Graphics[edit]
This integrated graphics includes an additional 128 MiB of eDRAM on-chip.
Integrated Graphics Information
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon E3-1558L v5 - Intel"
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |