From WikiChip
Difference between revisions of "intel/xeon e7/e7-2803"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
m (Bot: moving all {{mpu}} to {{chip}}) |
||
(2 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Xeon E7-2803}} | {{intel title|Xeon E7-2803}} | ||
− | {{ | + | {{chip |
| name = Xeon E7-2803 | | name = Xeon E7-2803 | ||
| no image = Yes | | no image = Yes | ||
Line 10: | Line 10: | ||
| model number = E7-2803 | | model number = E7-2803 | ||
| part number = AT80615006438AB | | part number = AT80615006438AB | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Server | | market = Server | ||
| first announced = April 5, 2011 | | first announced = April 5, 2011 | ||
Line 134: | Line 134: | ||
|avx=No | |avx=No | ||
|avx2=No | |avx2=No | ||
− | + | ||
|abm=No | |abm=No | ||
|tbm=No | |tbm=No |
Latest revision as of 15:28, 13 December 2017
Edit Values | ||||||||||||
Xeon E7-2803 | ||||||||||||
General Info | ||||||||||||
Designer | Intel | |||||||||||
Manufacturer | Intel | |||||||||||
Model Number | E7-2803 | |||||||||||
Part Number | AT80615006438AB | |||||||||||
S-Spec | SLC3M | |||||||||||
Market | Server | |||||||||||
Introduction | April 5, 2011 (announced) April 5, 2011 (launched) | |||||||||||
End-of-life | August 21, 2015 (last order) February 2, 2018 (last shipment) | |||||||||||
Release Price | $774.00 | |||||||||||
Shop | Amazon | |||||||||||
General Specs | ||||||||||||
Family | Xeon E7 | |||||||||||
Series | E7-2800 | |||||||||||
Locked | Yes | |||||||||||
Frequency | 1733.33 MHz | |||||||||||
Bus type | QPI | |||||||||||
Bus rate | 4.80 GT/s | |||||||||||
Clock multiplier | 13 | |||||||||||
CPUID | 206F2 | |||||||||||
Microarchitecture | ||||||||||||
Microarchitecture | Westmere | |||||||||||
Platform | Boxboro | |||||||||||
Chipset | Boxboro | |||||||||||
Core Name | Westmere EX | |||||||||||
Core Family | 6 | |||||||||||
Core Model | 47 | |||||||||||
Core Stepping | A2 | |||||||||||
Process | 32 nm | |||||||||||
Transistors | 2,600,000,000 | |||||||||||
Technology | CMOS | |||||||||||
Die | 513 mm² | |||||||||||
Word Size | 64 bit | |||||||||||
Cores | 6 | |||||||||||
Threads | 12 | |||||||||||
Max Memory | 1 TiB | |||||||||||
Multiprocessing | ||||||||||||
Max SMP | 2-Way (Multiprocessor) | |||||||||||
Electrical | ||||||||||||
Vcore | 1.35 V | |||||||||||
TDP | 105 W | |||||||||||
Tcase | 5 °C – 64 °C | |||||||||||
Tstorage | -40 °C – 85 °C | |||||||||||
Packaging | ||||||||||||
|
Xeon E7-2803 is a 64-bit hexa-core x86 data center microprocessor that supports up to 2 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.73 GHz with a TDP of 105 W but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory.
Contents
Cache[edit]
- Main article: Westmere § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Graphics[edit]
This SoC has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||||||
|
Facts about "Xeon E7-2803 - Intel"
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
max memory bandwidth | 23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) + |
max memory channels | 4 + |
supported memory type | DDR3-800 + |