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Latest revision as of 22:15, 12 November 2020

Edit Values
Intel Pentium P6100
General Info
DesignerIntel
ManufacturerIntel
Model NumberP6100
Part NumberCP80617004125AL
S-SpecSLBUR
MarketMobile
IntroductionSeptember 26, 2010 (announced)
September 26, 2010 (launched)
ShopAmazon
General Specs
FamilyPentium
SeriesP6000
LockedYes
Frequency1,999.99 MHz
Bus typeDMI 1.0
Bus rate1 × 2.5 GT/s
Clock multiplier15
CPUID0x20655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureWestmere
PlatformCalpella
ChipsetIbex Peak
Core NameArrandale
Core Family6
Core Model37
Core SteppingK0
Process32 nm
Transistors382,000,000
TechnologyCMOS
Die81 mm²
Word Size64 bit
Cores2
Threads2
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP35 W
Tjunction0 °C – 90 °C
Tstorage-25 °C – 125 °C
Packaging
PackagerPGA-988A (rPGA)rPGA988A.svg
Dimension36 mm x 35 mm x 2.12 mm
Pitch1 mm
Pin Count988
SocketSocket-G1 (PGA)
PackageBGA-1288 (BGA)BGA-1288.svg
Dimension34 mm x 28 mm x 2.1 mm
Pitch0.7 mm
Pin Count1288

Pentium P6100 is a 64-bit dual-core x86 mobile microprocessor introduced by Intel in 2010. This processor operates at a frequency of 2.00 GHz and a TDP of 35 W. This MPU is manufactured on a 32 nm process based on the Westmere microarchitecture (Arrandale core). This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 667.00 MHz.

Cache[edit]

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associativewrite-back
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB12-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3 12800s
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels2
Max Bandwidth15.88 GiB/s
16,261.12 MiB/s
17.051 GB/s
17,051.02 MB/s
0.0155 TiB/s
0.0171 TB/s
Bandwidth
Single 7.942 GiB/s
Double 15.88 GiB/s
Physical Address (PAE)36 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes16
Configs1x16


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics (Ironlake)
DesignerIntelDevice ID0x0046
Execution Units12Max Displays2
Frequency500 MHz
0.5 GHz
500,000 KHz
Burst Frequency667 MHz
0.667 GHz
667,000 KHz
Standards
DirectX10.1
OpenGL2.1
Additional Features
Intel Flexible Display Interface (FDI)
Intel Clear Video

Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/pentium_(2009)/p6100&oldid=98158"
Facts about "Pentium P6100 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Pentium P6100 - Intel#io +
device id0x0046 +
has ecc memory supportfalse +
has featureEnhanced SpeedStep Technology + and Flex Memory Access +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
integrated gpuHD Graphics (Ironlake) +
integrated gpu base frequency500 MHz (0.5 GHz, 500,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units12 +
integrated gpu max frequency667 MHz (0.667 GHz, 667,000 KHz) +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
max memory bandwidth15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) +
max memory channels2 +
max pcie lanes16 +
supported memory typeDDR3-1066 +